This brief presents a piecewise linear approximation of the nonlinear Wilson (NW) neuron model for the realization of an efficient digital circuit implementation. The accuracy of the proposed piecewise Wilson (PW) model is examined by calculating time domain signal shaping errors. Furthermore, bifurcation analyses demonstrate that the approximation follows the same bifurcation pattern as the NW model. As a proof of concept, both models are hardware synthesized and implemented on field programmable gate arrays, demonstrating that the PW model has a range of neuronal behaviors similar to the NW model with considerably higher computational performance and a lower hardware overhead. This approach can be used in hardware-based large scale biological neural network simulations and behavioral studies. The mean normalized root mean square error and maximum absolute error of the PW model are 6.32% and 0.31%, respectively, as compared to the NW model.

Journal Paper - IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 1, 2019 IEEE
DOI: 10.1109/TCSII.2018.2852598    ISSN: 1549-7747    » doi

In this paper we present a new image sensor architecture for fast and accurate compressive sensing (CS) of natural images. Measurement matrices usually employed in compressive sensing CMOS image sensors (CS-CIS) are recursive pseudo-random binary matrices. We have proved that the restricted isometry property (RIP) of these matrices is limited by a low sparsity constant. The quality of these matrices is also affected by the non-idealities of pseudo-random numbers generators (PRNG). To overcome these limitations, we propose a hardware-friendly pseudo-random ternary measurement matrix generated on-chip by means of class III elementary cellular automata (ECA). These ECA present a chaotic behaviour that emulates random CS measurement matrices better than other PRNG. We have combined this new architecture with a block-based CS smoothed-projected Landweber (BCS-SPL) reconstruction algorithm. By means of single value decomposition (SVD) we have adapted this algorithm to perform fast and precise reconstruction while operating with binary and ternary matrices. Simulations are provided to qualify the approach.

Journal Paper - IEEE Transactions on Circuits and Systems for Video Technology, first online, 2019 IEEE
DOI: 10.1109/TCSVT.2019.2892178    ISSN: 1051-8215    » doi

This paper presents a differential time-domain comparator formed by two voltage controlled delay lines, one per input terminal, and a binary phase detector for comparison solving. The propagation delay through the respective lines can be adjusted with a set of digitally-controlled inversion-mode varactors. These varactors provide tuning capabilities to the comparator; feature which can be exploited for offset calibration. This is demonstrated with the implementation of a differential 10-bit SAR-ADC. The design, fabricated in a 0.18μm CMOS process, includes an automatic mechanism for adjusting the capacitance of the varactors in order to calibrate the offset of the whole converter. Correct functionality was measured in all samples.

Journal Paper - IEEE Transactions on Circuits and Systems II: Express Brief, first online, 2019 IEEE
DOI: 10.1109/TCSII.2019.2904100    ISSN: 1549-7747    » doi

This paper presents a fast background calibration method for comparator offsets in pipeline ADCs and analyzes the practical considerations in a 1.8 V 0.18 μm 100Msps pipeline ADC with 15-bit resolution (74 dB-Signal-to-noise plus Distortion Ratio [SNDR]). A self-repairing (SR) thermometer-to-binary encoder is developed to deal with malfunctioning in presence of high comparator offsets greater than one-half least-significant bit (LSB). In this situation, the effective thresholds between two adjacent comparators could be inverted leading to a faulty behavior with conventional architectures. The proposed solution allows a dynamic assignment of the calibration code associated to each comparator improving convergence speed. As demonstrator, its application to a 15-bit pipeline ADC using a novel calibrated dynamic-latch comparator (DLC) with internal threshold reference generation and no preamplifier is presented, showing a reduction on the total power consumption of 22% with respect to a design without calibration targeting the same specifications.

Journal Paper - International Journal of Circuit Theory and Applications, vol. 47, no. 3, pp 333-349, 2019 JOHN WILEY & SONS
DOI: 10.1002/cta.2594    ISSN: 0098-9886    » doi

In safety critical applications there is a demand for estimating defect coverage in order to meet stringent quality levels. However, defect simulation of complex AMS-RF circuits is computationally expensive since achieving good confidence interval requires sampling many defects. In this paper, we show on practical cases of study that it is beneficial to complement defect coverage with fault coverage and assess the severity of defect escapes to get a complete picture of test quality. The computational burden of defect and fault simulations is taken into account and accurate statistical estimates of defect and fault escapes are provided to allow safe early stopping of the simulations.

Journal Paper - IEEE Transactions on Device and Materials Reliability, vol. 19, no. 1, pp 55-63, 2019 IEEE
DOI: 10.1109/TDMR.2019.2894534    ISSN: 1530-4388    » doi