Tunnel field-effect transistors (TFETs) are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of Complementary Metal Oxide Semiconductor (CMOS) technology. In this paper, we analyze the relationship between devices and register transfer-level architecture choices. We claim that architectural issues should be considered when evaluating this type of transistors because of the differences in delay versus supply voltage behavior exhibited by TFET logic gates with respect to CMOS gates. More specifically, the potential of pipelining and parallelism, both of which rely on lowering supply voltage, as power reduction techniques is evaluated and compared for CMOS and TFET technologies. The results obtained show significantly larger savings in power and energy per clock cycle for the TFET designs than for their CMOS counterparts, especially at low voltages. Pipelining and parallelism make it possibly to fully exploit the distinguishing characteristics of TFETs, and their relevance as competitive TFET circuit design solutions should be explored in greater depth.

Journal Paper - International Journal of Circuit Theory and Applications, first online, 2017 JOHN WILEY & SONS
DOI: 10.1002/cta.2398    ISSN: 0098-9886    » doi

RF to DC passive rectifiers can benefit from the superior performance at low voltage of tunnel transistors. They have shown higher power conversion efficiency (PCE) at low input power than Si FinFETs counterparts. In this paper, we analyze the limitations of typical TFET rectifier topologies associated with the forward biasing of their intrinsic diode and show that this can occur at relatively weak input signals depending on the specific characteristic of the used tunnel device. We propose a simple modification in the implementation of the rectifiers to overcome this problem. The impact of our proposal is evaluated on the widely used gate cross-coupled topology. The proposed designs exhibit similar peak PCE and sensitivity but significantly improve PCE for larger input signal amplitude and larger input power.

Journal Paper - IEEE Journal of the Electron Devices Society, first online, 2017 IEEE
DOI: 10.1109/JEDS.2017.2737598    ISSN: 2168-6734    » doi

The integration of lightweight symmetric encryption is becoming increasingly widespread in very low-power Internet of Things applications, with the rapid emergence of very low energy block and stream ciphers in portable and wireless systems. Trivium is one of the lightweight stream ciphers shortlisted for the hardware profile of the eSTREAM project. This paper describes low-power multiradix Trivium implementations based on the use of parallelization techniques to reduce dynamic power consumption. The low-power Trivium designs were implemented and characterized in TSMC 90 nm to compare area resources and power reduction. The implementation results show that our proposed designs offer dynamic power savings of 31%-45% with radix-1 and radix-2 when compared with the standard Trivium, and 15% with radix-8. There is no improvement, however, with radix-16.

Journal Paper - IEEE Transactions on Very Large Scale Integration (VLSI) Systems, first online, 2017 IEEE
DOI: 10.1109/TVLSI.2017.2736063    ISSN: 1063-8210    » doi

Address event representation (AER) is a widely employed asynchronous technique for interchanging "neural spikes" between different hardware elements in neuromorphic systems. Each neuron or cell in a chip or a system is assigned an address (or ID), which is typically communicated through a high-speed digital bus, thus time-multiplexing a high number of neural connections. Conventional AER links use parallel physical wires together with a pair of handshaking signals (request and acknowledge). In this paper, we present a fully serial implementation using bidirectional SATA connectors with a pair of low-voltage differential signaling (LVDS) wires for each direction. The proposed implementation can multiplex a number of conventional parallel AER links for each physical LVDS connection. It uses flow control, clock correction, and byte alignment techniques to transmit 32-bit address events reliably over multiplexed serial connections. The setup has been tested using commercial Spartan6 FPGAs attaining a maximum event transmission speed of 75 Meps (Mega events per second) for 32-bit events at a line rate of 3.0 Gbps. Full HDL codes (vhdl/verilog) and example demonstration codes for the SpiNNaker platform will be made available.

Journal Paper - IEEE Transactions on Biomedical Circuits and Systems, first online, 2017 IEEE
DOI: 10.1109/TBCAS.2017.2717341    ISSN: 1932-4545    » doi

Devices combining transistors and phase transition materials are being investigated to obtain steep switching and a boost in the I-ON/I-OFF ratio and, thus, to solve power and energy limitations of CMOS technologies. This paper analyzes the operation of circuits built with these devices. In particular, we use a recently projected device called hyper-FET to simulate different circuits, and to analyze the impact of the degraded dc output voltage levels of hyper-FET logic gates on their circuit operation. Experiments have been carried out to evaluate power of these circuits and to compare with counterpart circuits using FinFETs. The estimated power advantages from device level analysis are also compared with the results of circuit level measurements. We show that these estimations can reduce, cancel, or even lead to power penalties in low switching and/or low-frequency circuits. We also discuss relationships with some device level parameters showing that circuit level considerations should be taken into account for device design.

Journal Paper - IEEE Transactions on Electron Devices, vol. 64, no. 9, pp 3912-3918, 2017 IEEE
DOI: 10.1109/TED.2017.2726765    ISSN: 0018-9383    » doi