Noticias


Convocatoria Catedras PERTE Chip
Resuelta provisionalmente la convocatoria de Cátedras PERTE Chip

La Universidad de Sevilla consigue una Cátedra PERTE Chip (4,2M€), con la tercera mejor puntuación de 17 propuestas, con un proyecto liderado por profesores del IMSE y en cuyo equipo participan 39 investigadores de nuestro centro.
6 Marzo 2024

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Anuncio Tesis Doctoral
Anuncio Defensa Pública de Tesis Doctoral

El acto de defensa público de la Tesis Doctoral de D. Eros Camacho Ruiz en el marco del programa de doctorado de Ciencias y Tecnologías Físicas de la Universidad de Sevilla se celebrará el 13 de marzo del 2024 a las 11:00 horas en el Instituto de Microelectrónica de Sevilla.

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Premios FAMA
La US reconoce con los Premios FAMA a cinco de sus investigadores

El Prof. Ángel Rodríguez Vázquez ha sido galardonado con el Premio FAMA a la Trayectoria Investigadora y de Transferencia en el Área de Ingeniería y Arquitectura.
5 Marzo 2024

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Redes neuronales oscilatorias
Publicación en el blog La Cuadratura del Círculo

Las redes neuronales oscilatorias representan un emocionante paso adelante en nuestro viaje hacia la comprensión y la emulación de la complejidad del cerebro humano, y su impacto promete ser profundo y duradero.
Juan Núñez Martínez
1 Febrero 2024

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GoIT Panel IMSE
Actividad en el Proyecto GoIT

El próximo 14 de diciembre se realizará en el Salón de Grados del IMSE un panel sobre hardware de código abierto para construir componentes Root-of-Trust, como parte de nuestras actividades en el proyecto GoIT.
7 Diciembre 2023

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Ganador concurso Tesis 3 Minutos
Santiago Fernández Scagliusi gana el concurso Tesis en 3 Minutos en la US

Santiago Fernández Scagliusi, procedente del programa de doctorado en Ingeniería Informática, ha sido el ganador de la quinta edición del concurso Tesis en 3 Minutos de la Universidad de Sevilla. Su tesis fue codirigida por Pablo Pérez y Gloria Huertas, ambos pertenecientes al IMSE a la línea "Biomedical Circuits and Systems".
7 Diciembre 2023

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EVENTOS Y NOTICIAS ANTERIORES

Nueva Directora del IMSE-CNM


La investigadora del IMSE Teresa Serrano Gotarredona ha sido nombrada nueva Directora del Instituto de Microelectrónica de Sevilla.

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Formación en el IMSE


- Doctorado
- Máster
- Grados
- Trabajos Fin de Grado
- Prácticas en Empresa

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Publicaciones recientes


A Small-Area 2nd-Order Adder-Less Continuous-Time ΔΣ Modulator With Pulse Shaping FIR DAC for Magnetic Sensing
M. Srivastava, A. Ferro, A. Sidun, P. Cantillon-Murphy, Daniel O’Hare, K. O’Donoghue and J.M. de la Rosa
Journal Paper · IEEE Open Journal of Circuits and Systems (Early Access)
IEEE    ISSN: 2644-1225
resumen      doi      

This work presents a small-area 2nd-order continuous-time ΔΣ Modulator (CTΔΣM) with a single low dropout regulator (LDO) serving as both the power supply for the CTΔΣM and reference voltage buffer. The CTΔΣM is used for digitising very low amplitude signals in applications such as magnetic tracking for image-guided and robotic surgery. A cascade of integrators in a feed-forward architecture implemented with an adder-less architecture has been proposed to minimise the silicon area. In addition, a novel continuous-time pulse-shaped digital-to-analog converter (CT-PS DAC) is proposed for excess loop delay (ELD) compensation to simplify the current drive requirements of the reference voltage buffer. This enables a single low-dropout (LDO) voltage regulator to generate both power supply and Vref for the DAC. The circuit has been designed in 65-nm CMOS technology, achieving a peak 82-dB SNDR and 91-dB DR within a signal bandwidth of 20 kHz and the CTΔΣM consumes 300 μW of power when clocked at 10.24 MHz. The CTΔΣM achieves a state-of-the-art area of 0.07 mm.

A Control-Bounded Quadrature Leapfrog ADC
H. Malmberg, F. Feyling and J.M. de la Rosa
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers, 2024
IEEE    ISSN: 1549-8328
resumen      doi      

In this paper, the design flexibility of the control-bounded analog-to-digital converter principle is demonstrated. A band-pass analog-to-digital converter is considered as an application and case study. We show how a low-pass control-bounded analog-to-digital converter can be translated into a band-pass version where the guaranteed stability, converter bandwidth, and signal-to-noise ratio are preserved while the center frequency for conversion can be positioned freely. The proposed converter is validated with behavioral simulations on several filter orders, center frequencies, and oversampling ratios. Additionally, we consider an op-amp circuit realization where the effects of first-order op-amp non-idealities are shown. Finally, robustness against component variations is demonstrated by Monte Carlo simulations.

Reliability improvement of SRAM PUFs based on a detailed experimental study into the stochastic effects of aging
A. Santana-Andreo, P. Saraza-Canflanca, R. Castro-Lopez, E. Roca and F.V. Fernandez
Journal Paper · AEU - International Journal of Electronics and Communications, Volume 176, 155147, 2024
ELSEVIER    ISSN: 1434-8411
resumen      doi      

Physical Unclonable Functions (PUFs) have gained attention as a lightweight hardware security primitive. In particular, the SRAM-based PUF uses the unpredictable power-up value of the cells within an SRAM. Although these values should ideally be always the same within each SRAM to accomplish a correct PUF operation, this is often not the case, especially when factors like circuit aging are considered. While certain studies explore the effects of aging on SRAM PUFs, they often simplify the analysis. For instance, some studies assume that only Bias Temperature Instability (BTI) contributes to circuit degradation while others evaluate the overall degradation without accounting for the stochastic effects of aging on each individual cell. In this work, we first perform a detailed characterization of the nature of aging in SRAM PUFs, demonstrating that the impact of Non-Conductive Hot-Carrier Injection cannot be neglected. We also show that different cells degrade differently, highlighting the importance of accounting for the stochasticity of aging. After that, a method based on the Data Retention Voltage metric to select the cells with the most stable power-up response is introduced. Using these cells to generate the PUF identifier will result in a more stable response, and thus a better PUF performance.

On the Use of Artificial Neural Networks for the Automated High-Level Design of ΣΔ Modulators
P. Díaz-Lobo, G. Liñán-Cembrano and J.M. de la Rosa
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers, 2023
IEEE    ISSN: 1549-8328
resumen      doi      

This paper presents a high-level synthesis methodology for Sigma-Delta Modulators (ΣΔ Ms) that combines behavioral modeling and simulation for performance evaluation, and Artificial Neural Networks (ANNs) to generate high-level designs variables for the required specifications. To this end, comprehensive datasets made up of design variables and performance metrics, generated from accurate behavioral simulations of different kinds of ΣΔ Ms, are used to allow the ANN to learn the complex relationships between design-variables and specifications. Several representative case studies are considered, including single-loop and cascade architectures with single-bit and multi-bit quantization, as well as both Switched-Capacitor (SC) and Continuous-Time (CT) circuit techniques. The proposed solution works in two steps. First, for a given set of specifications, a trained classifier proposes one of the available ΣΔ M architectures in the dataset. Second, for the proposed architecture, a Regression-type Neural Network (RNN) infers the design variables required to produce the requested specifications. A comparison with other optimization methods - such as genetic algorithms and gradient descent - is discussed, demonstrating that the presented approach yields to more efficient design solutions in terms of performance metrics and CPU time.

TODAS LAS PUBLICACIONES

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Qué hacemos en el IMSE


El área de especialización del Instituto es el diseño de circuitos integrados analógicos y de señal mixta en tecnología CMOS, así como su uso en diferentes contextos de aplicación tales como dispositivos biomédicos, comunicaciones inalámbricas, conversión de datos, sensores de visión inteligentes, ciberseguridad, computación neuromórfica y tecnología espacial.

La plantilla del IMSE-CNM está formada por unas cien personas, entre personal científico y de apoyo, que participan en el avance del conocimiento, la generación de diseños de alto nivel científico-técnico y la transferencia de tecnología.

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