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Se buscan candidatos/as para un contrato de Titulado Superior en el área de Tecnología Electrónica y de Comunicaciones, asociado al Proyecto de Investigación n-PATETIC (Nuevos paradigmas para el test de circuitos integrados de señal mixta).  [+ info] »
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Se buscan candidatos/as para un contrato de Titulado Superior en el área de Tecnología Electrónica y de Comunicaciones, asociado al Proyecto de Investigación MARAGDA (Aproximación multi-nivel al diseño orientado a la fiabilidad de circuitos integrados analógicos y digitales).  [+ info] »
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Melania Rivers Rodríguez. Gerente del IMSE-CNM.
16 Febrero 2017
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Últimas publicaciones
Embedded electronic circuits for cryptography, hardware security and true random number generation: an overview  »
We provide an overview of selected crypto-hardware devices, with a special reference to the lightweight electronic implementation of encryption/decryption schemes, hash functions, and true random number generators. In detail, we discuss the hardware implementation of the chief algorithms used in private-key cryptography, public-key cryptography, and hash functions, discussing some important security issues in electronic crypto-devices, related to side-channel attacks (SCAs), fault injection attacks, and the corresponding design countermeasures that can be taken. Finally, we present an overview about the hardware implementation of true random number generators, discussing the chief electronic sources of randomness and the types of post-processing techniques used to improve the statistical characteristics of the generated random sequences.

Journal Paper - International Journal of Circuit Theory and Applications, vol. 45, no. 2, pp 145-169, 2017 JOHN WILEY & SONS
DOI: 10.1002/cta.2296    ISSN: 0098-9886    » doi
A.J. Acosta, T. Addabbo and E. Tena-Sánchez
Side-channel analysis of the modular inversion step in the RSA key generation algorithm  »
This paper studies the security of the RSA key generation algorithm with regard to side-channel analysis and presents a novel approach that targets the simple power analysis (SPA) vulnerabilities that may exist in an implementation of the binary extended Euclidean algorithm (BEEA). The SPA vulnerabilities described, together with the properties of the values processed by the BEEA in the context of RSA key generation, represent a serious threat for an implementation of this algorithm. It is shown that an adversary can disclose the private key employing only one power trace with a success rate of 100 % - an improvement on the 25% success rate achieved by the best side-channel analysis carried out on this algorithm. Two very different BEEA implementations are analyzed, showing how the algorithm's SPA leakages could be exploited. Also, two countermeasures are discussed that could be used to reduce those SPA leakages and prevent the recovery of the RSA private key.

Journal Paper - International Journal of Circuit Theory and Applications, vol. 45, no. 2, pp 199-213, 2017 JOHN WILEY & SONS
DOI: 10.1002/cta.2283    ISSN: 0098-9886    » doi
A. Cabrera Aldaya, R. Cuiman Márquez, A.J. Cabrera Sarmiento and S. Sánchez-Solano
Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs  »
Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this paper, the evaluation and the comparison of the performance of distinct fan-in logic gates, using a set of widely accepted power-speed metrics, are addressed for five projected tunnel transistor (TFET) technologies and four MOSFET and FinFET transistors. The impact of logic depth, switching activity and minimum supply voltage has been also included in our analysis. Provided results suggest that benefits in terms of a certain metric, in which a higher weight is placed on power or delay, are strongly determined by the selected device. Particularly, the suitability of two of the explored TFET technologies to improve CMOS performance for different metrics is pointed out. A circuit level benchmark is evaluated to validate our analysis.

Journal Paper - IEEE Transactions on Nanotechnology, vol. 16, no, 1, pp 83-89, 2017 IEEE
DOI: 10.1109/TNANO.2016.2629264    ISSN: 1536-125X    » doi
J. Núñez and M.J. Avedillo
Trivium hardware implementations for power reduction  »
This paper describes the use of parallelization techniques to reduce dynamic power consumption in hardware implementations of the Trivium stream cipher. Trivium is a synchronous stream cipher based on a combination of three non-linear feedback shift registers. In 2008, it was chosen as a finalist for the hardware profile of the eSTREAM project. So that their power consumption values can be compared and verified, the proposed low-power Trivium designs were implemented and characterized in 350-nm standard-cell technology with both transistors and gate-level models, in order to permit both electrical and logical simulations. The results show that the two designs decreased average power consumption by between 15% and 25% with virtually no performance loss and only a slight overhead (about 5%) in area.

Journal Paper - International Journal of Circuit Theory and Applications, vol. 45, no. 2, pp 188-198, 2017 JOHN WILEY & SONS
DOI: 10.1002/cta.2281    ISSN: 0098-9886    » doi
J.M. Mora-Gutiérrez, C.J. Jiménez-Fernández and M. Valencia-Barrero
An automated design methodology of RF circuits by using Pareto-optimal fronts of EM-simulated inductors  »
A new design methodology for radiofrequency circuits is presented that includes electromagnetic (EM) simulation of the inductors into the optimization flow. This is achieved by previously generating the Pareto-optimal front (POF) of the inductors using EM simulation. Inductors are selected from the Pareto front and their S-parameter matrix is included in the circuit netlist that is simulated using an RF simulator. Generating the EM-simulated POF of inductors is computationally expensive, but once generated, it can be used for any circuit design. The methodology is illustrated both for a single-objective and a multi-objective optimization of a Low Noise Amplifier.

Journal Paper - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 1, pp 15-26, 2017 IEEE
DOI: 10.1109/TCAD.2016.2564362    ISSN: 0278-0070    » doi
R. González-Echevarría, E. Roca, R. Castro-López, F.V. Fernández, J. Sieiro, J.M. López-Villegas and N. Vidal

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