Consejo Superior de Investigaciones Científicas · Universidad de Sevilla
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♦ Seminario IMSE-Forum
Metodología de marco lógico. Aplicación de la metodología de marco lógico como herramienta de planificación en la redacción de proyectos coherentes y viables, y recomendaciones para el desarrollo de ideas de proyectos.
Carmen Sánchez Ferrer, Project Manager del proyecto ACHIEVE-ITN (CSIC)
31 Enero 2019
Acto de Homenaje al Profesor José Luis Huertas, fundador y primer director del IMSE-CNM, con motivo del décimo aniversario del traslado al actual edificio. En el acto el Profesor Huertas impartió una charla sobre la historia del Instituto.
14 Diciembre 2018
♦ Defensa de Trabajos Fin de Máster
- Configurable Current Limitation Concept for Automotive Body Power Applications.
David Fernández Juanes
- Reguladores de tensión LDO de muy bajo consumo para aplicaciones de Energy Harvesting.
Óscar Pereira Rial
13 Diciembre 2018
♦ Visitas al IMSE
IES Inca Garcilaso
5 Diciembre 2018
Caracterización de Señales de Alta Velocidad: Fundamentos y Aplicaciones de Integridad de Señal.
29 Noviembre 2018

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Últimas publicaciones
A Multilevel Bottom-up Optimization Methodology for the Automated Synthesis of RF Systems  »
In recent years there has been a growing interest in electronic design automation methodologies for the optimizationbased design of radiofrequency circuits and systems. While for simple circuits several successful methodologies have been proposed, these very same methodologies exhibit significant deficiencies when the complexity of the circuit is increased. The majority of the published methodologies that can tackle radiofrequency systems are either based on high-level system specification tools or use models to estimate the system performances. Hence, such approaches do not usually provide the desired accuracy for RF systems. In this work, a methodology based on hierarchical multilevel bottom-up design approaches is presented, where multi-objective optimization algorithms are used to design an entire radiofrequency system from the passive component level up to the system level. Furthermore, each level of the hierarchy is simulated with the highest accuracy possible: electromagnetic simulation accuracy at device-level and electrical simulations at circuit/system-level.

Journal Paper - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, first online, 2019 IEEE
DOI: 10.1109/TCAD.2018.2890528    ISSN: 0278-0070    » doi
F. Passos, E. Roca, J. Sieiro, R. Fiorelli, R. Castro-López, J.M. López-Villegas and F.V. Fernández
On the implementation of asynchronous sun sensors  »
Abstract not avaliable

Conference - IS&T International Symposium on Electronic Imaging 2019
J.A. Leñero-Bardallo, R. Carmona-Galán and A. Rodríguez-Vázquez
On the Hardware Efficiency of 1-bit Homeostatic Stochastic STDP  »
Here we propose and demonstrate on FPGA hardware a homeostatic stochastic 1-bit weight STDP rule (whose 19 neurons have separate thresholds for integrating spikes and for triggering STDP update) used in a self-learning 20 feature extraction layer, which when combined with a rudimentary hebbian spiking classifier is capable of classifying with up to 100% accuracy a DVS recorded poker card symbol benchmark.

Conference - Cognitive Computing Conference 2018
A. Yousefzadeh, E. Stromatias, T. Serrano-Gotarredona and B. Linares-Barranco
Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits  »
The design of cryptographic circuits is requiring greater performance restrictions due to the constrained environments for IoT applications in which they are included. Focusing on the countermeasures based on dual-precharge logic styles, power, area and delay penalties are some of their major drawbacks when compared to their static CMOS single-ended counterparts. In this paper, we propose a initial study where scaled CMOS technnology and FinFET emerging technology are considered to foresee the relationship between ultra low power consumption, reduced delay, and security. As demonstration vehicle, we measure the performance and the security level achieved by different Substitution Boxes, implemented in different technologies. As main results, nanometer CMOS technologies maintains considerable security levels at reasonable power and delay figures, while FinFETs outperform CMOS in power and delay reduction, but with a non negligible degradation in security.

Conference - Conference on Design of Circuits and Integrated Systems DCIS 2018
E. Tena-Sánchez, I.M. Delgado-Lozano, J. Nuñez and A.J. Acosta
Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher  »
The fault injection in ciphers operation is a very successful mechanism to attack them. The inclusion of elements of protection against this kind of attacks is more and more necessary. These mechanisms are usually based on introducing redundancy, which leads to a greater consumption of resources or a longer processing time. This article presents how the introduction of placement restrictions on ciphers can make it difficult to inject faults by altering the clock signal. It is therefore a countermeasure that neither increases the consumption of resources nor the processing time. This mechanism has been tested on FPGA implementations of the Trivium cipher. Several tests have been performed on a Spartan 3E device from Xilinx and the experimental measurements have been carried out with ChipScope Pro. The tests showed that an adequate floorplanning is a good countermeasure against these kind of attacks.

Conference - Conference on Design of Circuits and Integrated Systems DCIS 2018
F.E. Potestad-Ordóñez, C.J. Jiménez-Fernández, M. Valencia-Barrero, C. Baena and P. Parra

Webs relacionadas con el IMSE
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martes, 22 de enero de 2019
Última actualización: 17.01.2019
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