The best way to learn how to design digital systems at the RT level is to use practical examples. In addition, from a teaching point of view, the more practical they are, the more attractive to students. But for a design to be attractive, even if it is presented with a low complexity, it is not possible to do it in a single practice session. This paper presents, as a demonstrator, the design at RT level and its implementation in FPGA of a digital system that uses the Trivium flow cipher and on which measurements of maximum operating frequency are made. This circuit is designed in three laboratory sessions of about two hours each.

Conference - Congreso de Tecnologia, Aprendizaje y Enseñanza de la Electronica TAEE 2018

Digital design learning at the RT level requires practical examples and as learning progresses, the examples need to become more complex. FPGAs and development boards offer a very suitable platform for the implementation of these designs. However, classroom practice sessions usually last two hours, which does not allow the complexity of the designs be high enough. For this reason, interesting designs that can be made in several sessions are required In this paper, the construction of a distance measuring system is presented as a demonstrator. For this purpose, a distance measurement module based on ultrasound is available and the results are displayed in 7-segment displays on a Nexys4 board.

Conference - Congreso de Tecnologia, Aprendizaje y Enseñanza de la Electronica TAEE 2018

This demo showcases a low-cost smart camera where different hardware configurations can be selected to perform image recognition on deep neural networks. Both the hardware configuration and the network model can be changed any time on the fly. Up to 24 hardware-model combinations are possible, enabling dynamic reconfiguration according to prescribed application requirements.

Conference - ACM International Conference on Distributed Smart Cameras ICDSC 2018 DOI: 10.1145/3243394.3243705    » doi

In computational neuroscience, synaptic plasticity learning rules are typically studied using the full 64-bit floating point precision computers provide. However, for dedicated hardware implementations, the precision used not only penalizes directly the required memory resources, but also the computing, communication, and energy resources. When it comes to hardware engineering, a key question is always to find the minimum number of necessary bits to keep the neurocomputational system working satisfactorily. Here we present some techniques and results obtained when limiting synaptic weights to 1-bit precision, applied to a Spike-Timing-Dependent-Plasticity (STDP) learning rule in Spiking Neural Networks (SNN). We first illustrate the 1-bit synapses STDP operation by replicating a classical biological experiment on visual orientation tuning, using a simple four neuron setup. After this, we apply 1-bit STDP learning to the hidden feature extraction layer of a 2-layer system, where for the second (and output) layer we use already reported SNN classifiers. The systems are tested on two spiking datasets: a Dynamic Vision Sensor (DVS) recorded poker card symbols dataset and a Poisson-distributed spike representation MNIST dataset version. Tests are performed using the in-house MegaSim event-driven behavioral simulator and by implementing the systems on FPGA (Field Programmable Gate Array) hardware.

Journal Paper - Frontiers in Neuroscience, vol. 12, article 665, 2018 FRONTIERS RESEARCH FOUNDATION
DOI: 10.3389/fnins.2018.00665    ISSN: 1662-4548    » doi

In this paper, surrogate modeling techniques are applied for passive component modeling. These techniques are exploited to develop and compare two alternative strategies for automated radio-frequency circuit design. The first one is a traditional approach where passive components are designed during the optimization stage. The second one, inspired on bottom-up circuit design methodologies, builds passive component Pareto-optimal fronts (POFs) prior to any circuit optimization. Afterward, these POFs are used as an optimized library from where the passive components are selected. This paper exploits the advantages of evolutionary computation algorithms in order to efficiently explore the circuit design space, and the accuracy and efficiency of surrogate models to model passive components.

Journal Paper - IEEE Transactions on Very Large Scale Integration Systems, vol. 26, no. 11, pp 2386-2394, 2018 IEEE
DOI: 10.1109/TVLSI.2018.2859827    ISSN: 1063-8210    » doi