Consejo Superior de Investigaciones Científicas · Universidad de Sevilla
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El IMSE-CNM en Digital.CSIC


 
Publicaciones recientes
Embedded electronic circuits for cryptography, hardware security and true random number generation: an overview
A.J. Acosta, T. Addabbo and E. Tena-Sánchez
Journal Paper - International Journal of Circuit Theory and Applications, vol. 45, no. 2, pp 145-169, 2017
JOHN WILEY & SONS    DOI: 10.1002/cta.2296    ISSN: 0098-9886    » doi
[abstract]
We provide an overview of selected crypto-hardware devices, with a special reference to the lightweight electronic implementation of encryption/decryption schemes, hash functions, and true random number generators. In detail, we discuss the hardware implementation of the chief algorithms used in private-key cryptography, public-key cryptography, and hash functions, discussing some important security issues in electronic crypto-devices, related to side-channel attacks (SCAs), fault injection attacks, and the corresponding design countermeasures that can be taken. Finally, we present an overview about the hardware implementation of true random number generators, discussing the chief electronic sources of randomness and the types of post-processing techniques used to improve the statistical characteristics of the generated random sequences.

Side-channel analysis of the modular inversion step in the RSA key generation algorithm
A. Cabrera Aldaya, R. Cuiman Márquez, A.J. Cabrera Sarmiento and S. Sánchez-Solano
Journal Paper - International Journal of Circuit Theory and Applications, vol. 45, no. 2, pp 199-213, 2017
JOHN WILEY & SONS    DOI: 10.1002/cta.2283    ISSN: 0098-9886    » doi
[abstract]
This paper studies the security of the RSA key generation algorithm with regard to side-channel analysis and presents a novel approach that targets the simple power analysis (SPA) vulnerabilities that may exist in an implementation of the binary extended Euclidean algorithm (BEEA). The SPA vulnerabilities described, together with the properties of the values processed by the BEEA in the context of RSA key generation, represent a serious threat for an implementation of this algorithm. It is shown that an adversary can disclose the private key employing only one power trace with a success rate of 100 % - an improvement on the 25% success rate achieved by the best side-channel analysis carried out on this algorithm. Two very different BEEA implementations are analyzed, showing how the algorithm's SPA leakages could be exploited. Also, two countermeasures are discussed that could be used to reduce those SPA leakages and prevent the recovery of the RSA private key.

Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs
J. Núñez and M.J. Avedillo
Journal Paper - IEEE Transactions on Nanotechnology, vol. 16, no, 1, pp 83-89, 2017
IEEE    DOI: 10.1109/TNANO.2016.2629264    ISSN: 1536-125X    » doi
[abstract]
Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this paper, the evaluation and the comparison of the performance of distinct fan-in logic gates, using a set of widely accepted power-speed metrics, are addressed for five projected tunnel transistor (TFET) technologies and four MOSFET and FinFET transistors. The impact of logic depth, switching activity and minimum supply voltage has been also included in our analysis. Provided results suggest that benefits in terms of a certain metric, in which a higher weight is placed on power or delay, are strongly determined by the selected device. Particularly, the suitability of two of the explored TFET technologies to improve CMOS performance for different metrics is pointed out. A circuit level benchmark is evaluated to validate our analysis.

Trivium hardware implementations for power reduction
J.M. Mora-Gutiérrez, C.J. Jiménez-Fernández and M. Valencia-Barrero
Journal Paper - International Journal of Circuit Theory and Applications, vol. 45, no. 2, pp 188-198, 2017
JOHN WILEY & SONS    DOI: 10.1002/cta.2281    ISSN: 0098-9886    » doi
[abstract]
This paper describes the use of parallelization techniques to reduce dynamic power consumption in hardware implementations of the Trivium stream cipher. Trivium is a synchronous stream cipher based on a combination of three non-linear feedback shift registers. In 2008, it was chosen as a finalist for the hardware profile of the eSTREAM project. So that their power consumption values can be compared and verified, the proposed low-power Trivium designs were implemented and characterized in 350-nm standard-cell technology with both transistors and gate-level models, in order to permit both electrical and logical simulations. The results show that the two designs decreased average power consumption by between 15% and 25% with virtually no performance loss and only a slight overhead (about 5%) in area.

An automated design methodology of RF circuits by using Pareto-optimal fronts of EM-simulated inductors
R. González-Echevarría, E. Roca, R. Castro-López, F.V. Fernández, J. Sieiro, J.M. López-Villegas and N. Vidal
Journal Paper - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 1, pp 15-26, 2017
IEEE    DOI: 10.1109/TCAD.2016.2564362    ISSN: 0278-0070    » doi
[abstract]
A new design methodology for radiofrequency circuits is presented that includes electromagnetic (EM) simulation of the inductors into the optimization flow. This is achieved by previously generating the Pareto-optimal front (POF) of the inductors using EM simulation. Inductors are selected from the Pareto front and their S-parameter matrix is included in the circuit netlist that is simulated using an RF simulator. Generating the EM-simulated POF of inductors is computationally expensive, but once generated, it can be used for any circuit design. The methodology is illustrated both for a single-objective and a multi-objective optimization of a Low Noise Amplifier.

An inductor modeling and optimization toolbox for RF circuit design
F. Passos, E. Roca, R. Castro-López and F.V. Fernández
Journal Paper - ntegration, the VLSI Journal, first online, 2016
ELSEVIER    DOI: 10.1016/j.vlsi.2017.01.009    ISSN: 0167-9260    » doi
[abstract]
This paper describes the SIDe-O toolbox and the support it can provide to the radio-frequency designer. SIDe-O is a computer-aided design toolbox developed for the design of integrated inductors based on surrogate modeling techniques and the usage of evolutionary optimization algorithms. The models used feature less than 1% error when compared to electromagnetic simulations while reducing the simulation time by several orders of magnitude. Furthermore, the tool allows the creation of S-parameter files that accurately describe the behavior of inductors for a given range of frequencies, which can later be used in SPICE-like simulations for circuit design in commercial environments. This toolbox provides a solution to the problem of accurately and efficiently optimizing inductors, which alleviates the bottleneck that these devices represent in the radio-frequency circuit design process.

Brownian distance correlation-directed search: A fast feature selection technique for alternate test
G. Leger and M.J. Barragan
Journal Paper - Integration, the VLSI Journal, vol. 55, pp 401-414, 2016
ELSEVIER    DOI: 10.1016/j.vlsi.2016.05.003    ISSN: 0167-9260    » doi
[abstract]
Machine-learning indirect test relies on powerful statistical algorithms to build prediction models that relate cheap measurements to costly performance metrics. Though many works in the past have been focused on proposing different models or on ways to improve the reliability of the results, it appears that the main bottleneck of the approach is the definition of an information-rich input space. Finding the appropriate measurements that are both cheap and meaningful is a task that has not yet been automated. In this framework, feature selection is a necessary tool to explore possible candidates. In this paper a hybrid method is proposed that lay between filtering and wrapper-based methods, trying to strike the right balance between accuracy and speed for the particular case of Alternate Test.

A dual-factor access control system based on device and user intrinsic identifiers
R. Arjona and I. Baturone
Conference - IEEE Industrial Electronics Conference IECON 2016
[abstract]
This paper proposes an access control system based on the simultaneous authentication of what the user has and who the user is. At enrollment phase, the wearable access device (a smart card, key fob, etc.) stores a template that results from the fusion of the intrinsic device identifier and the user biometric identifier. At verification phase, both the device and user identifiers are extracted and matched with the stored template. The device identifier is generated from the start-up values of the SRAM in the device hardware, which are exploited as a Physically Unclonable Function (PUF). Hence, if the device hardware is cloned, the authentic identifier is not generated. The user identifier is obtained from level-1 fingerprint features (directional image and singular points), which are extracted from the fingerprint images captured by the sensor in the access device. Hence, only genuine users with genuine devices are authorized to access and no sensitive information is stored or travels outside the access device. The proposal has been validated by using 560 fingerprints acquired in live by an optical sensor and 560 SRAM-based identifiers.

Physical unclonable keys for smart lock systems using Bluetooth Low Energy
M.A. Prada-Delgado, A. Vázquez-Reyes and I. Baturone
Conference - IEEE Industrial Electronics Conference IECON 2016
[abstract]
Nowadays, several smart lock systems use Bluetooth Low Energy (BLE) to stablish a wireless communication between the physical key (key fob, card, smartphone, etc.) and the lock. Security is based on creating and storing secret digital keys to establish a cryptographically secure communication. The problem is that several attacks can break such security, particularly the copy of the physical key. In order to increase the difficulty of the attacks, the physical keys described in this paper do not store the secret cryptographic keys but reconstruct them when they are needed and remove them when they are not used. Only the trusted physical keys are able to reconstruct the secrets with the public data stored in them. This is possible by using the start-up values of the SRAM in the BLE chip of the physical key, which acts as a physical unclonable function (PUF), so that if the physical key is copied, the lock cannot be opened. The idea has been proven with the development of a smart lock system with key fobs based on the CC2541 BLE system on chip from Texas Instruments. Experimental results are included to illustrate the performance.

Live demonstration: High-level optimization of ΣΔ modulators using multi-objetive evolutionary algorithms
M. Velasco-Jiménez, R. Castro-López and J.M. de la Rosa
Conference - IEEE International Symposium on Circuits and Systems, ISCAS 2016
[abstract]
This demo shows how to use multi-objective evolutionary algorithms for the optimum high-level design of ΣΔ analog-to-digital converters. The methodology illustrated in the demo is based on the combination of SIMSIDES, a SIMULINK-based time-domain behavioral simulator for ΣΔ modulators, with multi-objective optimization techniques. The proposed methodology allows designers to explore the design space in an efficient and intuitive way in order to fulfill a number of different design objectives simultaneously, by finding out the best sets of target specifications - defined as Pareto-optimal fronts. The presented approach can be extended to several kinds of optimizers implemented in MATLAB, and diverse examples are illustrated so that visitors will learn how to apply it to their own designs and projects. Although the demo is focused on ΣΔ ADCs, the tools shown in the demo can be used for the optimization of any other analog integrated circuits and systems.

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