Consejo Superior de Investigaciones Científicas · Universidad de Sevilla
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A Multilevel Bottom-up Optimization Methodology for the Automated Synthesis of RF Systems
F. Passos, E. Roca, J. Sieiro, R. Fiorelli, R. Castro-López, J.M. López-Villegas and F.V. Fernández
Journal Paper - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, first online, 2019
IEEE    DOI: 10.1109/TCAD.2018.2890528    ISSN: 0278-0070    » doi
[abstract]
In recent years there has been a growing interest in electronic design automation methodologies for the optimizationbased design of radiofrequency circuits and systems. While for simple circuits several successful methodologies have been proposed, these very same methodologies exhibit significant deficiencies when the complexity of the circuit is increased. The majority of the published methodologies that can tackle radiofrequency systems are either based on high-level system specification tools or use models to estimate the system performances. Hence, such approaches do not usually provide the desired accuracy for RF systems. In this work, a methodology based on hierarchical multilevel bottom-up design approaches is presented, where multi-objective optimization algorithms are used to design an entire radiofrequency system from the passive component level up to the system level. Furthermore, each level of the hierarchy is simulated with the highest accuracy possible: electromagnetic simulation accuracy at device-level and electrical simulations at circuit/system-level.

On the implementation of asynchronous sun sensors
J.A. Leñero-Bardallo, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - IS&T International Symposium on Electronic Imaging 2019
[abstract]
Abstract not avaliable

On the Hardware Efficiency of 1-bit Homeostatic Stochastic STDP
A. Yousefzadeh, E. Stromatias, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - Cognitive Computing Conference 2018
[abstract]
Here we propose and demonstrate on FPGA hardware a homeostatic stochastic 1-bit weight STDP rule (whose 19 neurons have separate thresholds for integrating spikes and for triggering STDP update) used in a self-learning 20 feature extraction layer, which when combined with a rudimentary hebbian spiking classifier is capable of classifying with up to 100% accuracy a DVS recorded poker card symbol benchmark.

Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits
E. Tena-Sánchez, I.M. Delgado-Lozano, J. Nuñez and A.J. Acosta
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2018
[abstract]
The design of cryptographic circuits is requiring greater performance restrictions due to the constrained environments for IoT applications in which they are included. Focusing on the countermeasures based on dual-precharge logic styles, power, area and delay penalties are some of their major drawbacks when compared to their static CMOS single-ended counterparts. In this paper, we propose a initial study where scaled CMOS technnology and FinFET emerging technology are considered to foresee the relationship between ultra low power consumption, reduced delay, and security. As demonstration vehicle, we measure the performance and the security level achieved by different Substitution Boxes, implemented in different technologies. As main results, nanometer CMOS technologies maintains considerable security levels at reasonable power and delay figures, while FinFETs outperform CMOS in power and delay reduction, but with a non negligible degradation in security.

Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher
F.E. Potestad-Ordóñez, C.J. Jiménez-Fernández, M. Valencia-Barrero, C. Baena and P. Parra
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2018
[abstract]
The fault injection in ciphers operation is a very successful mechanism to attack them. The inclusion of elements of protection against this kind of attacks is more and more necessary. These mechanisms are usually based on introducing redundancy, which leads to a greater consumption of resources or a longer processing time. This article presents how the introduction of placement restrictions on ciphers can make it difficult to inject faults by altering the clock signal. It is therefore a countermeasure that neither increases the consumption of resources nor the processing time. This mechanism has been tested on FPGA implementations of the Trivium cipher. Several tests have been performed on a Spartan 3E device from Xilinx and the experimental measurements have been carried out with ChipScope Pro. The tests showed that an adequate floorplanning is a good countermeasure against these kind of attacks.

Single Event Transient injection in large mixed-signal circuits
V. Gutierrez and G. Leger
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2018
[abstract]
Abstract not avaliable

SAR ADCs with Redundant Split-capacitor DAC
A. Lopez-Angulo, A. Gines, E. Peralias and A. Rueda
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2018
[abstract]
This paper analyzes the effect of redundancy in Successive Approximation Register (SAR) ADCs with splitcapacitor DAC (Split-CDAC). It also presents a general hardware-based model which provides closed-relationships, suitable for design, between the capacitor scale factors, the bridge capacitance and the practical implementation of the digital correction logic. In conventional binary Split-CDAC (without redundancy), the voltage at the floating nets in the array could exceed the ADC references, stressing the operation of switches. Using the proposed model, we will show that this effect also occurs in SAR ADCs with redundancy, but with some particularities depending on the selection of the weighting coefficients in the digital correction logic. We will demonstrate the excursion can be controlled, as in the binary case, with a simple DAC modification which includes an extra limiting capacitor.

A 2-MS/s, 11.22 ENOB, extended input range SAR ADC with improved DNL and offset calculation
S. Asghar, S. Saadat Afridi, A. Pillai, A. Schuler, J.M. de la Rosa and I. O'Connell
Conference - International Symposium on Integrated Circuits and Systems ISICAS 2018
[abstract]
A 12-bit successive approximation register analog-to-digital converter (ADC) with extended input range is presented. Employing an input sampling scaling technique, the presented ADC can digitize the signals with an input range of 3.2 Vpp-d (± 1.33 VREF). The circuit also includes a comparator offset compensation technique that results in a residual offset of less than 0.5 LSB. The chip has been designed and implemented in a 0.13-µm CMOS process and demonstrates the state-of-the-art performance, featuring an SNDR of 69.3 dB and the SFDR of 79 dB without requiring any calibration. Total power consumption of the ADC is 0.9 mW, with a measured differential non-linearity of 1.2/-1.0 LSB and INL of 2.3/-2.2 LSB.

Asynchronous spiking pixel with programmable sensitivity to illumination
J.A. Leñero-Bardallo, M. Delgado-Restituto, R. Carmona-Galan and A. Rodriguez-Vazquez
Conference - International Symposium on Integrated Circuits and Systems ISICAS 2018
[abstract]
A spiking pixel to be used in image sensor arrays for asynchronous frame-based operation is presented. The pixel features both local and global adaptive sensitivity to the illumination level. Local adaptation is performed by adjusting the voltage stored in an embedded analog memory according to the average illumination within a neighborhood. Global adaptation to the overall illumination of the array is implemented by adjusting a voltage value common to all the pixels. These programming capabilities allow full control on the sensor sensitivity, pixel output data flow, and energy consumption, thus, overcoming the limitations observed in current image sensors based on spiking pixels. Experimental results validate the functionality of the proposal.

Inverting Versus Non-Inverting Dynamic Logic for Two-Phase Latch-free Nanopipelines
H.J. Quintero, M. Jimenez, M.J. Avedillo and J. Núñez
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
[abstract]
Very fine grained latch-free pipelines are successfully used in critical parts of high performance systems. These approaches are based in Domino logic and multi-phase clock schemes. Reducing the number of logic levels per clock phase and the number of phases to the minimum is a potential way to push the limits of speed. However the implementation of such architectures with just one logic level per clock phase and two clock phases is a challenge which requires extremely full-custom design and exhibits robustness concerns. In this paper we show that the non-inverting feature of Domino plays a critical role in these difficulties. We analyze and compare the performance of two-phase gate-level pipelines implemented with Domino and with ILP, an inverting dynamic gate we have proposed. Our experiments confirm that ILP pipelines are much more robust and could simplify design.

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