Techniques will be investigated to analyze and model digital noise generation and its impact on ADC performance. Design techniques will be developed to reduce the noise generation as well as the impact of digital noise on the performance of the ADC.

A general design for test methodology will be developed for high-speed mixed-signal ASICs consisting of a high-speed ADC and a fast, multirate DSP block. The developed methodologies will be demonstrated and evaluated by means of an integrated circuit design for an industrial telecom application.

Another objective is to investigate the limits of embedded ADC performance in a standard 0.35 um digital CMOS technology and to advance the achievable performance by solving the problems caused by the mixed-signal integration. Targeted specifications are at least 50 Msamples/s, resolution up to 10 bit and maximum effective resolution bandwidth with a low power consumption. However, a number of the methodologies being investigated in this project are more generally applicable to the integration of other analog blocks of mixed-signal receivers (as well as transmitters) or even mixed-signal ASICs in application domains other than telecom.

• Development of a simulation/analysis methodology to investigate the impact of substrate switching noise generated by digital circuits on the performance of analog circuits embedded on the same substrate. Emphasis is on the modeling of the noise generated by a complex digital circuit and on the modeling of the impact of substrate noise on the performance of analog circuits.
• Development of design techniques to reduce the substrate noise coupling in mixed-signal ASICs. Design techniques will be investigated to reduce the noise generated by a large digital circuit. At the same time analog design techniques and ADC architectures for reduced noise sensitivity will be developed.
• Development of a design for test methodology for high-speed embedded analog-to-digital converters.