The trend of industrial demand for A/D converters is that of high performance in terms of resolution and speed at the same time, with the constraints of optimized power consumption and low supply voltage. In addition to the difficulty of such challenging analog design specifications, an A/D converter will be affected by all non-ideal effects inherently present in a mixed-signal circuit requiring fast and complex digital processing associated to a sensitive analog functionality. The parasitic coupling of the digital switching noise generated by the digital section of the circuit will be the limiting factor for the resolution. Moreover, this effect becomes increasingly restrictive in deep submicron technology.

In mixed-mode applications digital signal processing sections are usually implemented using conventional CMOS static logic which is known to generate a large amount of switching noise. The existing methods used for reducing the effects of digital switching noise are mainly protective or defensive, such as shielding, symmetry and fully differential analog techniques.

In this project, in addition to these known techniques, an active method that decreases the parasitic coupling between analog and digital sections is proposed. Our choice is to use a new logic family, the CSL approach, whose characteristics make CSL very suitable for mixed-signal design.

The main advantages of CSL are:

• More than 40 dB switching noise reduction compared to standard static logic
• Reduced logic swing, suitable for low supply voltage operation
• High tolerance to technological fluctuations

• To develop a fully characterized Current Steering Logic (CSL) library as well as its design  methodologies dedicated to mixed-signal industrial applications using a 0.35 mm digital CMOS technology. Two versions of this library will be provided, one designed for low power applications, and another for high frequency applications.
• To realize three A/D Converters for modern applications such as audio codec, wireless communication systems, and video, respectively :

16-bit Low-Voltage S-D ADC
Low-Power, Low-Voltage, 12-bit, 1 MHz, Nyquist Rate ADC
A True 12-bit, 25 MSample/s Pipelined ADC
• To compare CSL to standard static logic approach. This comparison will be done by integrating two versions of each ADCs : one using CSL and the other standard static logic.

Project results: three mixed-signal products based on low noise digital environment

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