ESD-MSD Mixed
Signal Design Cluster
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ESD-MSD Mixed
Signal Design Cluster
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| Summary | |
| The present evolutions in VLSI technology allow
in the near future to integrate entire systems on a single die, comprising
both embedded processors, memories, logic blocks, but also some analogue
blocks like data converters. The implementation of such mixed-signal systems
poses some specific problems. First of all, their design requires a new
system-on-a-chip design methodology that allows mapping an application-specific
algorithm to a system-level architecture using system-level trade-off and
exploration tools. Secondly, the implementation of these systems suffers
from parasitic interactions, e.g. the large parameter tolerances of modern
sub-micrometer technologies, which have to be carefully analyzed and included
in the design, both at system and at circuit level. This therefore requires
a detailed analysis and modeling of nonidealities. Thirdly, the detailed
verification of entire mixed-signal systems is not possible at the transistor
level. Instead, higher levels of modeling have to be used, also for the
analogue blocks, in order to be able to simulate the system performance
in acceptable CPU times. It is therefore crucial to develop accurate yet
efficient behavioral models for analogue blocks as needed in system verifications.
Such an accurate executable model is also needed if the analogue block
is to be reused in several different applications or with other customers
than the originating design group. In that case not a transistor schematic
is the kind of information that must accompany the macrocell but rather
a simulatable behavioral model that can be used in system simulations (comparable
to a timing-accurate VHDL model for a digital module).
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| Main Objectives | |
| The SysConv project contributes to the above requirements
by developing a system-level model for oversampling delta-sigma converters
that can be used in mixed-signal system simulations and verifications.
The existing work in industry and academia has addressed the modeling of
different converter architectures in terms of the subblocks and their parameters.
However, this work does not address the development of a model of the entire
converter as a block on its own, that can then be used in efficient mixed-signal
system simulations where the converter is only a block in the overall system.
Such work has already been done for Nyquist-rate converters but to our
knowledge not yet for oversampling delta-sigma converters. This is exactly
the advancement that this project tries to achieve.
In order to make this possible, a good understanding of the nominal performance of oversampling delta-sigma converters as well as their major nonidealities, from the point of view of a system block, is needed. Hence, the major nonidealities present in oversampling converters will be analyzed and described. Furthermore, existing information on system models will be used wherever possible and available. This knowledge will then be used to develop an accurate system-level model, together with the corresponding set of extraction routines to extract the model parameters from a lower level implementation. The work will also lead to an advanced top-down design methodology for oversampling delta-sigma converters based on the highly accurate models of the analogue building blocks. Due to the inclusion of major linear and nonlinear nonidealities in the models a high design security will be achieved resulting in a first-silicon-success strategy. Hence, a target of the project will be the incorporation of this methodology in the mixed-signal design environments of the partners. The whole approach will be demonstrated by means of real converter designs and fabricated silicon samples. |
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| Project Duration | |
| Start | July 1998 |
| End | December 2000 |
| Coordinator | Infineon Technologies, Germany |
| Partner | Katholieke Universiteit Leuven, Belgium |
Last update: February 12, 2001