Presentations
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Title
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Project
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Authors
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Design of Low-Power Digital
Filter Through Simulated Evolution
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Presentation (PDF, 813
kB)
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Notes (PDF, 123 kB)
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MIXMODEST |
M. Erba
R. Rossi
V. Liberali
A. G. B. Tettamanzi |
Current Steering Logic: From Gates to Applications
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Presentation (PDF, 457 kB)
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Notes (ZIP,
478 kB)
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HIPADS |
M. Kayal
M. Pastre |
Efficient and Accurate Simulation of
Substrate Noise Generation by Large Digital Circuits
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Presentation (PDF,
4103 kB)
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Notes (PDF, 4 kB)
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BANDIT |
M. van Heijningen
M. Badaroglu |
Modeling of Impact of Digital Substrate
Noise on the Performance of Analog Circuits
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Presentation (PDF, 328
kB)
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Notes (PDF, 9 kB)
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BANDIT |
Y. Zinzius |
Reusability Methodology for IC Layouts
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Presentation Part I (PDF,
815 kB)
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Notes Part I (PDF, 49 kB)
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Presentation Part II (PPT,
1280 kB)
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Notes Part II (PDF, 733 kB)
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RAPID |
R. Castro
M. Delgado
F. V. Fernández
A. Rodríguez-Vázquez
J. Vital
Jing Nan Xu |
Automated Sizing and Retargetting of
Basic Building Blocks
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Presentation (PDF, 1593
kB)
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RAPID |
F. V. Fernández
F. Medeiro
R. Domínguez-Castro
A. Rodríguez-Vázquez |
| DAISY: A Simulation-Based High-Level Synthesis
Tool for S-D Modulators
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SYSCONV |
K. Francken
G. Gielen |
CAD Methodology for High-Resolution,
High-Speed S-D Modulators with Emphasis in Cascade Multi-Bit Architectures
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Presentation (PDF, 1116 kB)
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MIXMODEST |
F. Medeiro
R. del Río
J.M. de la Rosa
B. Pérez Verdú
A. Rodríguez-Vázquez |
| Design
of Low-Power Digital Filter Through Simulated Evolution |
| |
Although digital filter design methodology is well established,
the technological trend in silicon integration is now demanding for new
CAD tools, to increase designer productivity and to cope with increased
integration density. The larger and larger number of devices, integrated
onto a single silicon chip, not only leads to increased computational power
and increased frequency performance, but also increases power consumption,
which is expected to be a major problem for integrated circuit designers
in the next decade. Since power consumption is non-linear and input pattern
dependent, its minimisation is a difficult task.
This presentation illustrates an evolutionary approach to the
design of a finite impulse response digital filter with reduced power consumption.
The proposed design approach combines genetic optimization and simulation
methodology, to evaluate a multi-objective fitness function which includes
both the suitability of the filter transfer function and the digital transition
activity of elementary cells, the latter being responsible for power consumption.
Examples on some design cases are presented and discussed.
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| Current
Steering
Logic: from the Gate to the Applications |
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Standard static CMOS logic is responding to the requirement
of high frequency and low power of digital systems. However, the digital
switching noise generated by this logic is not suited for the design of
performance mixed-signal integrated systems. In mixed-signal application,
the analog functionality can be affected by this digital switching noise
and therefore resolution is degraded. The Current Steering Logic (CSL)
is one of the well-known techniques capable of decreasing the switching
noise. Despite its static power consumption, the CSL is considered as a
promising approach to achieve a good functionality in some mixed-signal
application.
In this seminar a summary of the following topics will be presented:
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Review of CSL performance criteria as well as a design methodology specific
to this logic family.
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Discussion of design flow adopted to implement CSL gate layouts.
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Example of CSL using in the implementation of a digital algorithm employed
in an offset compensation scheme for a CMOS operational amplifier.
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Presentation and demonstration of two standalone PC CAD tools dedicated
to automatic design and layout for deep sub-micron CSL libraries
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| Efficient
and Accurate Simulation of Substrate Noise Generation by Large Digital
Circuits |
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More and more system-on-chip designs require the integration
of analog circuits on large digital ICs. This mixed-signal integration
will degrade the performance of the integrated analog circuit. One of the
major causes of this performance degradation is substrate noise coupling.
To analyse the performance of the integrated analog circuits an accurate
simulation of the substrate noise generated by the digital circuits is
necessary. For large digital circuit this simulation can no longer be done
at transistor level. Therefore we have developed a high-level Substrate
Noise Waveform Analysis tool (SWAN) that can efficiently and accurately
simulate the substrate noise generation of large digital circuits.
The first part of the presentation will focus on the low-level
models on which the high-level tool is based. The low-level analysis of
substrate noise generation is done at SPICE level, by adding a SPICE substrate
model to each standard cell circuit. These SPICE models have been verified
by measurements on a mixed-signal test IC. These models have also been
used to analyze the dominant sources of substrate noise generation in digital
circuits. The substrate noise generation is analyzed both in the time and
frequency domain and is related to the digital clock frequency and package
parasitics.
The second part will focus on the Substrate Waveform Analysis
(SWAN) methodology, which enhances a VHDL simulation using a substrate
macro-cell library created once for each standard cell. Each substrate
macro-cell contains one current source for the supply current and one for
the noise current through the bulk node of the standard cell. The total
digital circuit composed of those substrate macro-cells is automatically
reduced to an equivalent substrate model at chip level including the package
parasitics. This equivalent substrate model is then simulated using our
event-driven based substrate noise simulator with the switching activity
information obtained from a gate-level VHDL simulation of the total digital
circuit. The total substrate voltage computed from this simulation can
then be connected to the substrate node of a sensitive analog circuit to
see the impact of the noise. Our SWAN methodology gives large speedups
compared to SPICE based substrate noise simulations while retaining a good
accuracy. The simulations have been verified with substrate noise measurements
on an 86 Kgate digital circuit.
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| Modeling
of Impact of Digital Substrate Noise on the Performance of Analog Circuits |
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In modern telecommunications IC's the number of mixed-signal
circuits is increasing. In these mixed-signal IC's the analog parts are
affected by the noise injected in the substrate by the digital part. To
provide a good estimation of the noise injected in the substrate some high-level
modelling tools are available, but to provide a complete high-level modelling
environment a modelling of the analog part should be also made. The methodology
presented will give the possibility to model the effects on analog design
of the substrate noise generated by the digital part.
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| Reusability
Methodology for IC Layouts |
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As chip complexity explodes and compressed product development
cycles relentlessly escalate time-to-market pressures, designers must accomplish
more in less time. For an increasing number of designers, the secret to
quickly building highly integrated systems on a chip (SoC) in a shrinking
development cycle lies in the extensive reuse of silicon-proven mega-functions
or blocks.
In this context, fundamentally new design paradigms have to
be found which will provide a very significant increase of the design productivity
that can be achieved today. This is particularly more important in
the area of analog and mixed analog-digital designs where the levels of
design automation are well behind what can already be achieved in the digital
domain. Retargetability for reuse can significantly increase the design
productivity of complex mixed-signal, specially having in mind the need
to achieve very short cycles of technology migration.
One of the most important aspects of those design reuse methodologies
implies the exploitation of layout views and the development of retargetable
analog-digital blocks that allow easy re-usability for different technology
environments and application requirements. This talk introduces new methodologies
for the retargetable layout design of a mixed-signal application-driven
quadrature D/A interface sub-system, aiming at its reusability by a retargeting
procedure with minimal changes to their structural sub-blocks.
In particular, two complementary methods for generation and reusability
of physical layouts of analog and mixed-signal blocks will be discussed.
The first method addresses the construction of a library of reusable
cells. The requirements to convert conventional cells into reusable cells
are different for the case of change of specifications and change of technology.
The second method concerning the reusability of an existing layout of a
given circuit block is based on new, template defined, layout reproduction
techniques.
Both methodologies have been built on top of commercially available
software packages within the Cadence DFWII environment.
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| Automated
Sizing and Retargeting of Basic Building Blocks |
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The continuously increasing demand of analog interfaces in mixed-signal
ASICs constitutes a challenge for today's IC designers. This is mainly
due to the need to produce fine (high resolution, high frequency, low power
consumption, small area) analog blocks in adverse digital technologies,
with reduced supply voltages and poor analog performance devices, which
are often deficiently modeled. In addition, this must be achieved in a
noisy environment due to the presence of a large amount of digital circuitry.
All these changes must be assimilated at the vertiginous rate
imposed by the technology and market evolution. Because of that, the traditional
approach to the analog design: analytical study + electrical simulation,
may be not enough. This has motivated the interest for supplying CAD tools
which can assist the design procedure to allow obtaining satisfactory designs
in very short times. Focusing our attention on the lowest level of the
design hierarchy, the automation of the electrical design of building blocks
has been a recursive topic in literature. With more or less success, a
set of strategies has been adopted, ranging from knowledge-based to optimization-based,
and from equation-based to simulation-based approaches. Among the different
possibilities, it is now accepted that combining optimization (statistical
and deterministic) and electrical simulation is one of the best approaches
because the accurate electrical simulation is probably the only way to
ensure the viability of the sized cells per construction.
In this presentation a methodology for automated circuit sizing
will be described. This methodology incorporates both statistical and deterministic
optimization techniques in combination with an electrical simulator.
It also contains a knowledge library with allows the reuse of circuit specific
knowledge, as well as, the easy addition of new knowledge for existing
or new circuit topologies. Two applications scenarios will be introduced.
The first one addresses design of building blocks starting from scratch.
The second one is devoted to retargeting of existing designs to new specifications
and/or new silicon technologies, and incorporating physical design constraints.
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| DAISY:
A Simulation-Based High-Level Synthesis Tool for SD Modulators |
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An integrated tool (DAISY: Delta-Sigma Analysis and Synthesis)
is presented for the high-level synthesis of SD modulators. The approach
determines simultaneously the optimum modulator topology and the required
building block specifications, such that the system specifications - mainly
in terms of accuracy and signal bandwidth - are satisfied at the lowest
possible total power consumption. A genetic-based differential evolution
algorithm is used in combination with a fast dedicated behavioral simulator
that includes the major non-idealities of the building blocks to realistically
analyze and optimize the modulator performance.
The proposed tool has, to the best of our knowledge, the most
integrated functionality (simulation, post-processing, visualization and
optimization are all seamlessly integrated) compared to tools found in
the open literature. Moreover, the synthesis procedure uses fast behavioral
models to accurately simulate the moves suggested by the optimizer. The
optimizer itself is a genetic-based differential evolution algorithm. It
simultaneously generates several vectors during each generation so that
superior candidates can help to escape local minima.
This new approach will allow a design engineer to select the
most appropriate topology for a specific set of specifications and also
returns the minimum required specifications for the building blocks taking
all the non-idealities into account so that the systemrequirements are
satisfied and the power minimized. It is then possible to verify the obtained
results in the same software environment.
A comparison with a state-of-the-art design is presented and
illustrates the effec-tiveness of the approach. Also, an extensive set
of topology optimizations has been performed for a wide range of specifications
showing the capabilities of the tool.
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| CAD
Methodology for High-Resolution, High-Speed SD Modulators with Emphasis
in Cascade Multi-bit Architectures |
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During the last few years it has been shown that the combination
of high-order cascade (MASH) architectures with multi-bit quantization
provides a viable strategy to combine high-speed and high-resolution without
calibration needed . These modulators gather the unconditional stability
of cascade modulators (whenever only second- and/or first-order stages
are used) and the advantages of multi-bit quantization with a relaxed requirement
for the linearity of the latter. The feasibility and efficiency of this
approach, because it needs no correction/calibration mechanism, have been
proved in analog technologies.
However, because some circuit imperfections as for example finite
opamp DC gain and capacitor mismatching can hide some of the benefits of
multi-bit quantization, particularly for the low values of the oversampling
ratio compatible with high-frequency operation, the design problem must
be carefully tackled specially in digital sub-micron technologies where
degradation of both MOSFET output conductance and capacitor matching is
more than foreseeable.
In this arena, the methodological issues are of prime importance
for reaching an efficient implementation at the state-of-the-art performance
edges in an acceptably short design cycle. As an answer to this necessity,
a CAD methodology aimed for assisting the design of high-performance SD
Ms is presented. It fits the commonly adopted hierarchical design approach
comprising: (a) transmission of the modulator specifications down to the
building block specifications (high-level synthesis); (b) advanced behavioral
simulation for specification fine-tuning and verification; and (c) transmission
of the cell specifications down to device sizes (cell-level synthesis).
This methodology is illustrated here through the design of a
4th-order 2-1-1 cascade multi-bit S-D modulator featuring 14bit@4MSample/s
aimed for xDSL applications. The modulator has been implemented in a 0.35um
mainstream digital CMOS technology with the objective of minimum power
consumption. Architecture selection, modulator sizing and cell sizing were
supported and optimized by the CAD tools, while the full-custom layout
was done manually.
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