In the first part, the fundamental processes on analog-to-digital conversion are presented: uniform and non-uniform quantization with their respective performance, sampling, sampling under Shannon condition, downsampling and downconversion, SNR improvement by oversampling, by noise shaping, quantization noise, encoding.

In the second part of the presentation, a classification of  the most well-known A/D converter architectures  is proposed and each A/D converter type is analyzed highlighting the advantages and disadvantages, the attainable resolution-speed-consumption ranges as well as the limits, the potential drawbacks, the sensitivity to deep submicron technology implementation.

After a brief survey on most important specifications of data converters with respect to their utilization, some practical applications are analyzed in the data acqusition, voice, audio and wireless domain.

As a design example the design of a 6-bit CMOS analog-to-digital converter (A/D) with a maximum acquisition speed of 1 GHz will be discussed. The problem of meta-stability has got special attention in this design, since this problem degrades the Spurious-Free Dynamic Range (SFDR) at these high sampling frequencies. 

Although initially employed for audio, the pros of SDM-based converters have motivated designers to explore their usage for frequency bands up to telecom and even video. Obviously, because the sampling frequency is ultimately limited by technology, it forces using moderate values of the oversampling ratio in order to achieve the signal bandwidth required for these applications - well into the MHz range. Consequently, the second-order phenomena becomes more and more important for these frequencies forcing designers to carefully select the modulator architectures as well as to optimize the many trade-offs that appear during the design process.

In order to circumvect these problems a number of solutions have appeared at both the architectural and the circuit design level. The latter include the use of pipelining, parallelization, casdading, etc. This contribution overviews these new architectures and outlines the major circuit design issues, with special emphasis on the limitations existing in conventional, digital CMOS technologies.

This project will draw on the results of the ESPRIT Mixed Signal project 'Video Decoder Platform' to show how sigma delta ADCs can be used in video rate applications. Current video products have signal bandwidths of 6 to 7 MHz and required signal to noise ratios of up to 60 dB. A small amount of oversampling is already employed in practice, so that conversion rates of 20 MHz to 30 MHz are not uncommon.

In general, existing video analog to digital converters are based on the switched capacitor 'pipeline'  architecture. The paper will discuss a number of important similarities between pipeline ADCs and existing broadband sigma delta ADCs. Modifications to the sigma delta architecture, which  are in principle quite simple, and which extend it's performace to higher signal bandwidths, will be presented. In particular, the architecture of an area and power efficient 72 dB SNR, 6.75 MHz  sigma delta with an oversampling rate of 8, will be presented.

However, circuit imperfections affecting cascade modulators can hide some of the benefits of multi-bit quantization. Particularly, finite opamp dc-gain and integrator weight mismatch cause incomplete cancellation of low-order shaped quantization error, which in its turn may degrade the dynamic range. This problem must be carefully tackled for the implementation of multi-bit cascade Sigma-Delta Modulators in digital submicron technologies where degradation of both MOSFET output conductance and capacitor matching is more than foreseeable.

This contribution analyzes the critical issues above from the point of view of their incidence on architecture selection, an presents a systematic top-down methodology for optimum design of these modulators.

In this work, some specific circuit techniques have been used to reach both resolution and high-speed requirements such as:

A continuous-time implementation has been preferred to the usual switched-capacitor techniques.

Modulator stability is achieved by taking special care on the different delays introduced by analog sub-blocks.

The digital-to-analog converter where the linearity is critical in the case of a multibit modulator uses a new ping-pong technique to reduce glitch effects during clock transitions.

A novel approach for opamps implementation has been used to achieve a high open loop gain with a large bandwidth.

In the first section, a comparison of different Delta-Sigma architectures (single-loop, cascaded or MASH, multi-bit) is presented. This results in the choice of a third order 4-bit converter. The main problem of multi-bit Delta-Sigma converters is the linearity requirement of the DAC in the feedback loop. Several techniques to alleviate these problems such as dynamic element matching and dual quantization will be discussed.

The second part treats the design aspects of a third order 4-bit Delta-Sigma converter. The converter employs dynamic element matching techniques to reduce the linearity requirements of the DAC. Several design aspects concerning the different building blocks will be discussed, focusing on the main differences with the design of classical single-bit Delta-Sigma converters. Finally, a short comparison to other high-performance Delta-Sigma converters will be shown.

This work is related to a video decoder platform, which uses a multi-bit sigma-delta converter to achieve 12 bit resolution at video data rates. One important aspect in the design of this type of high-speed, high resolution data converters, is the realisation of the reference voltage. In order to identify performance limiting factors caused by the reference section, an in-depth analysis of system and design issues was carried out.

The presentation covers the following topics related to the design of the reference section for high-speed embedded data converters in a 0.25 micron CMOS process.

Review of topologies for the reference voltage supply. Implications of an approach based on a fast reference buffer versus a slow reference buffer with external buffer capacitor.

Analysis of the effect of the lead-frame inductance on the impedance of the reference voltage in the case of a slow reference buffer. Extraction of a detailed model for the reference impedance.

Effect of the reference impedance on the integrator settling performance. Modelling of interstage cross-coupling effects. Optimisation of an on-chip RC-damping network.

Review and choice of an optimum topology for the reference buffer. Detailed analysis of design implications. 

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PART 1: "High-level Modeling and Simulation of Digital Noise Generation" (M. Badaroglu)

Substrate noise caused by large digital circuits degrades the performance of analog circuits sharing the same substrate. It is important to be able to model and simulate the amount of noise at a certain point on the substrate coming from complex digital circuits in mixed-mode circuits.

Existing approaches usually extract the model of the substrate from the  layout information and then simulate this extracted transistor-level netlist with its substrate model using a transistor-level simulator. Transistor-level simulation of complex digital systems with detailed substrate models  is not feasible due to large CPU requirements. In this presenation, we will discuss our Substrate Waveform ANalysis (SWAN) methodology which enhances the VHDL simulation flow with the use of a macromodel library based on the characterization of the substrate model for each standard cell. In this way the substrate noise generated by complex digital systems, taking into account the power supply noise, can be simulated from a system substrate macro model of the total digital circuit. Our SWAN methodology gives large speedups compared to traditional transistor-level substrate noise simulations while retaining a good accuracy.

PART 2: Evaluation of The Substrate Noise Effect on Analog Circuits in Mixed-Signal  Designs (Y. Zinzius)

We describe an approach to simulate the bulk in such a way that we can  evaluate the substrate noise effect on analog designs. To do such simulations  some tool are available in order to extract a substrate model and to add this  model to SPICE netlist. But the main disadvantage of this tool is the CPU time,  and memory required for the extraction.

For these simulations a simple model is used in order to reduce the time needed for the simulations. In  this model we take into account the effect of the bonding wire and the bulk  resistance. This simulation technique was applied to a Sample and Hold. 

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