Market trend is towards integration of home-based services and hand-held electronic products. Communication systems are playing the leading role, offering new broadband services, either wireless or wire-based. Low-cost and high-performance circuits are required to be competitive in a more and more demanding consumer market. Single chip solutions reduce costs and power consumption, and increase reliability. Moreover, they can help to reduce weight and size of hand-held electronic products.

In mixed systems, performance limitations come mainly from the analog section which interfaces the digital processing core with the external world. In addition to the difficult task of designing state-of-the-art analog-digital interfaces, mixed analog-digital microintegrated circuits offer an additional challenging aspect. In such ICs, coupling from switching digital nodes and noisy power supplies to analog devices through the common substrate is a serious limitation to analog circuit performance.

This presentation illustrates the problems arising when designing accurate analog-digital interfaces to be integrated into the same chip together with a digital processor. The generation of digital disturbs, their propagation through the substrate and their effects on analog devices are considered, with a particular emphasis on integrated circuits realized on heavily-doped substrate, where traditional shielding is less effective.

Techniques to reduce analog-digital crosstalk are discussed. Reduction of the effects coming from digital noise can be achieved in four different ways:

• by reducing the disturb injected into the substrate by means of a low-power digital design;
• by inserting shields between analog and digital sections, to attenuate the injected noise;
• by designing analog structures which have low sensitivity to digital noise;
• by using suitable assembling techniques.

Experimental results on a test chip are presented to validate the modeling approach.

First, the substrate noise generation of this test circuit has  been  measured, using the on-chip substrate noise sensor, both in the time and frequency domain. The frequency domain measurements show that most  substrate noise is generated at multiples of the digital clock  frequency, with noise peaks up to 40 dB above the noise floor. Next, a  SPICE-level substrate model has been added to the original digital  circuit description and the noise generation has been simulated. These results match very well with the measurements. Finally, using the SPICE  circuit and substrate model, an analysis has been done on the dominant  generation mechanism of the substrate noise generation, as function of  the package parasitics. Depending on these parasitics, either the noise generation of the MOSFETs themselves or the noise coupling from the digital power supply is the dominant source of substrate noise generation.