The focus of applications is in the area of automotive electronics, data communications and wireless telecommunications. An important goal of the activities is the creation of a seamless and tool-supported design method for sigma-delta converters as these play a crucial role in most application areas covered by this proposal. The composition of the consortium, with partners and subcontractors from the fields of system/semiconductor manufacturers, universities, applied research institutes, and CAD providers, enables improvements in EDA to be realized which specifically target the relevant applications. 

The talk will give an overview of the ANASTASIA+ structure and contents and focus on reuse activities. These activities address problems of automated documentation of models and IP block descriptions on one hand, and layout reuse by re-synthesis or compaction-based migration on the other hand. 
 

This talk will provide an overview in the project and its current progress. In particular, it will highlight the developed and planned activities in the area of mixed-signal reuse 

Layout created by placement tools usually shows a deficit in area minimization. Layout compaction is a convenient method to reach higher layout density, but it is restricted by the missing capability of conventional compaction engines to change generated modules. 
The situation on design reuse is quite similar: Beside the enforcement of changed design rule sets 
new or structural modified devices need to be inserted into layout. Compaction engines are capable to produce design rule conform layout; changes of leaf cell devices is not supported. This is a deficit in technology migration using compaction tools today. The combination of device substitution and compaction is the basic approach to solve this problem. New or changed devices may be built manually or generated automatically, optionally stored in a library, and then inserted by the device substitution algorithm integrated into the compaction engine. Subsequent the compaction process moves all layout components to their minimum distance. The devices may be different in size. In particular, the new generated device may be larger than the substituted. However, the topology of devices needs to be similar, e.g. the pin order must remain the same. 

New in this method is the inclusion of module generators. Generated devices can be transferred to the target technology by calling a generator out of the compaction engine. As a precondition, all device parameters for the generator call need to be accessible. Device parameters may be adopted from the original devices, or defined by the user via property. Thus, device parameters may be changed, if necessary.It is not recommended to change devices parameters by decision of a compaction algorithm. A placement tool should do this task using property information. 

In this article the analog capable compaction engine and its cooperation with module generators and a placement tool is presented. With CAMBIO-XT, a compaction engine with integrated device substitution is available. Besides its existing integrations into the Mentor and Cadence environments, CAMBIO-XT has been combined with the layout tool Paris/MGEN, with the enhanced capability to call MGEN module-generators. The detail placer TINA as part of the Paris/MGEN environment has been modified in its functionality: TINA now is able to process a layout without changing layout structure and to find out possible device parameters supporting chip area minimization. These parameters are transmitted to the compaction engine for the call of MGEN. These improvements have been developed in the german research project ELAN. In the Medea+ project ANASTASIA+, the abilities of CAMBIO-XT for analog/mixed-signal layout reuse are evaluated and optimized.

These high-level models will incorporate  different non-ideal effects. They can be realized taking into account different abstraction levels: device level, block level, etc., but  the description must be realized considering different aspects such as  modularity, reusability and parameterisation. These main factors will be analysed for mixed-signal in general and will be applied in the modelling of  a Pipeline ADC  as case study.

DS2 has developed a high speed communcation technology and it is working on more complex and  powerful designs. In the ToolIP project, we are working on the design flow  for mixed-signal IP blocks, and the co-design methologies for simulation and verification.

The methodology is based on three fundamental concepts: analog behavioral modeling, simulation-based design tuning and parameterized layout templates. Integration of electrical and physical design levels has been achieved by introducing layout parasitics early in the electrical tuning stage as well as a set of geometrical constraints to enhance the quality (in terms of area and symmetries) of the final layout solution. With those measures, the proposed methodology can be successfully applied and good results are obtained in one or two reuse cycles. 

In addition, it is possible to cope with the evolution of the technological processes since each element in this methodology (such as behavioral models, netlist descriptions or layout templates) has been made technology-independent by using speci?c methods. Experimental results from the application of the methodology to the analog back-end of an I/Q digital-to-analog conversion port, show that the effort needed to build up the knowledge database related to a given IP block is compensated by the intensive reuse of it.