Spanish National Research Council · University of Seville
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The Instituto de Microelectrónica de Sevilla welcomes postdoctoral candidates interested in applying for a Marie Skłodowska-Curie Individual Fellowships (MSCA-IF).
Offer Deadline: 20/08/2020 09:00 - Europe/Brussels
♦ Doctoral Thesis defense
Diseño de circuitos integrados para interfaces neuronales implantables.
José Luis Valtierra Sánchez de la Vega
June 10, 2020
♦ Doctoral Thesis defense
Design of CMOS Digital Silicon Photomultipliers with ToF
for Positron Emission Tomography.
Franco Nahuel Bandi
May 29, 2020
IMSE-CNM researchers Bernabé Linares Barranco and Teresa Serrano Gotarredona talk about how Neuromorphic Engineering seeks to replicate the functioning of the human nervous system with the intention of solving complex problems in real time and with greater energy efficiency. Technology Section of the newspaper El País.
April 14, 2020

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Recent publications
A 10-MHz BW 77.3-dB SNDR 640-MS/s GRO-based CT MASH ΣΔ Modulator  »
We present in this paper a novel multi-stage noise-shaping (MASH) 3-1 continuous-time (CT) delta-sigma modulator (ΣΔM) with gated ring oscillator based quantizers (GROQs) in both stages of the cascade. The use of GROQs increases the linearity performance with respect to the conventional voltage controlled oscillator based quantizers (VCOQs) and allows a more robust extraction of the front-end stage quantization error in the time domain, thus making the proposed architecture more suitable to implement high-order expandable scaling-friendly MASH ΣΔMs, in which the back-end stages are implemented by mostly-digital GRO-based time-to-digital converters (TDCs). The circuit has been fabricated in a 65-nm CMOS technology with 1-V supply voltage, and it operates at 640-MHz sampling frequency to digitize 10-MHz signals. To the best of the authors’ knowledge, this is the first reported experimental validation of a GRO-based CT MASH ΣΔM, featuring a 79.8-dB signal to noise ratio (SNR) at -2.2-dBFS, a 77.3-dB signal to (noise + distortion) ratio (SNDR) at -4-dBFS and a dynamic range (DR) of 81.7 dB, with a power consumption of 12-mW. These metrics demonstrate state-of-the-art performance with a DR-based Schreier FOM of 170.9 dB.

Journal Paper - IEEE Transactions on Circuits and Systems II: Express Briefs, first online, 2020 IEEE
DOI: 10.1109/TCSII.2020.2998727    ISSN: 1549-7747    » doi
M. Honarparvar, J.M. de la Rosa and M. Sawan
A Sub-µW Reconfigurable Front-End for Invasive Neural Recording that Exploits the Spectral Characteristics of the Wideband Neural Signal  »
This paper presents a sub- µW ac-coupled reconfigurable front-end for invasive wideband neural signal recording. The proposed topology embeds filtering capabilities enabling the selection of different frequency bands inside the neural signal spectrum. Power consumption is optimized by defining specific noise targets for each sub-band. These targets take into account the spectral characteristics of wideband neural signals: local field potentials (LFP) exhibit l/f(x) magnitude scaling while action potentials (AP) show uniform magnitude across frequency. Additionally, noise targets also consider electrode noise and the spectral distribution of noise sources in the circuit. An experimentally verified prototype designed in a standard 180 nm CMOS process draws 815 nW from a 1 V supply. The front-end is able to select among four different frequency bands (modes) up to 5 kHz. The measured input-referred spot-noise at 500 Hz in the LFP mode (1 Hz - 700 Hz) is 55 nV/root Hz while the integrated noise in the AP mode (200 Hz - 5 kHz) is 4.1 µVrms. The proposed front-end achieves sub-µW operation without penalizing other specifications such as input swing, common-mode or power-supply rejection ratios. It reduces the power consumption of neural front-ends with spectral selectivity by 6.1x and, compared with conventional wideband front-ends, it obtains a reduction of 2.5x.

Journal Paper - IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 5, pp 1426-1437, 2020 IEEE
DOI: 10.1109/TCSI.2020.2968087    ISSN: 1549-8328    » doi
J.L. Valtierra, M. Delgado-Restituto, R. Fiorelli and A. Rodriguez-Vazquez
Implementing Cryptographic Pairings on ARM dual-core Processors  »
In this paper, we explore the parallelization capabilities of the ARM processing system embedded in a Zynq device for a software implementation of the optimal Ate pairing. First, the use of the NEON coprocessor was evaluated. It was found that on ARM v7 Cortex-A9 processors the computation of the optimal Ate pairing based on NEON does not perform better than an optimized ARM-assembly equivalent implementation. Therefore, we moved to explore the parallelization of pairing computation using a dual-core processing approach. By organizing operations of line evaluation and point arithmetic formulas to have little data dependency, it was possible to schedule independent operations to be perfomed simultaneously in separate cores of an ARM dual-core Cortex-A9 processor. The same principle was applied in the arithmetic procedures of the extension fields. In this way, our software is able to perform 25.6% and 6.6% faster than the best two implementations previously reported on ARM Cortex-A9 processors.

Journal Paper - IEEE Latin America Transactions, vol. 18, no. 2, pp 232-240, 2020 IEEE
DOI: 10.1109/TLA.2019.9082233    ISSN: 1548-0992    » doi
R. Caiman, A. Cabrera and S. Sanchez-Solano
A comparative study of stacked-diode configurations operating in the photovoltaic region  »
This article presents a detailed comparative analysis of two possible stacked-diode configurations operating as solar cells. The performance of a single p-well - deep n-well diode is compared with the combination of such diode with a n-diff - pwell diode in parallel. Both configurations occupy the same area but offer different performance and, accordingly, they can have different application scopes. A test circuit to gauge the diodes performance and their spectral sensitivity has been integrated along with the two diode configurations in a 0.18 μm CMOS standard fabrication technology. The measured experimental results for the two diode configurations under study are validated with an analytical diode physical model.

Journal Paper - IEEE Sensors Journal, first online, 2020 IEEE
DOI: 10.1109/JSEN.2020.2987393    ISSN: 1530-437X    » doi
R. Gómez-Merchán, D. Palomeque-Mangut, J.A. Leñero-Bardallo, M. Delgado-Restituto and A. Rodríguez-Vázquez
On the use of causal feature selection in the context of machine-learning indirect test  »
The test of analog, mixed-signal and RF (AMS-RF) circuits is still considered as a matter of human creativity, and although many attempts have been made towards their automation, no accepted and complete solution is yet available. Indeed, capturing the design knowledge of an experienced analog designer is one of the key challenges faced by the Electronic Design Automation (EDA) community. In this paper we explore the use of causal inference tools in the context of AMS-RF design and test with the goal of defining a methodology for uncovering the root causes of performance variation in these systems. We believe that such an analysis can be a promising first step for future EDA algorithms for AMS-RF systems.

Conference - Design Automation and Test in Europe DATE 2020
M.J. Barragan, G. Leger, F. Cilici, E. Lauga-Larroze, S. Bourdel and S. Mir

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Friday, 05 June 2020
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