Spanish National Research Council · University of Seville
INTRANET  |  WEB MAIL
es    en
News
♦ Doctoral Thesis defense
Circuit design for biomedical laboratories based on bioimpedance measurement.
Pablo Peréz García
July 15, 2019
Bridging ICT and Medical Technologies for Smart Disease Diagnosis.
Myung Hoon Sunwoo, Ultra-small-sized Diagnostic and Smart Devices (uDSD) Research Center.
June 28, 2019  ·  10:00h.
The company Digilent Inc, in collaboration with the Seville Institute of Microelectronics and the Escuela Politécnica Superior of the Universidad de Sevilla will give the following workshops in June.
- Accelerate real-time high definition video processing designs with Digilent Zybo Z7, a Zynq-7000 AP SoC Platform and Xilinx Vivado HLS.
- Hands-on experimentation using Digilent Analog Discovery 2. Complete analog & digital circuits in or out of the lab.
June 17-18, 2019
♦ Mac Van Valkenburg Award 2019
Dr. Ángel Rodríguez Vázquez, researcher at the IMSE-CNM and professor at the Universidad de Sevilla, has been recipient of the Mac Van Valkenburg Award for fundamental contributions to mixed-signal chip architectures for smart imaging, vision and 2-D data processing. The award is based on the quality and significance of contribution, and continuity of technical leadership.. The awards ceremony will take place in the ISCAS 2019 Conference on May 28, 2019.

Job offers at IMSE

The World of Chips

IMSE offers a number of services based on the Agilent 93000 ATE platform

IMSE in the media

Information leaflet

The IMSE in Linkedin

IMSE in Linkedin

The IMSE in Digital.CSIC

IMSE in Digital.CSIC

Recent publications
Guest Editorial: Special Section on the 48th European Solid-State Circuits Conference (ESSCIRC)  »
This Special Section of the IEEE Journal of Solid-State Circuits (JSSC) features expanded versions of papers selected from those presented at the 48th ESSCIRC Conference, held at Technische Universität Dresden, Dresden, Germany, during September 3-6, 2018.

Journal Paper - IEEE Journal of Solid-State Circuits, vol. 54, no. 7, pp 1827-1829, 2019 IEEE
DOI: 10.1109/JSSC.2019.2919403    ISSN: 0018-9200    » doi
A. Rodriguez-Vazquez, K. Sengupta and S. Rusu
Yield recovery of mm-wave power amplifiers using variable decoupling cells and one-shot statistical calibration  »
Integrated millimeter-wave (mm-wave) circuits fabricated in current nanometric processes are especially sensitive to process variations. This issue produces shifts in the circuit performance that may significantly reduce the fabrication yield. In this line, per-die characterization and trimming are usually required for mm-wave integrated circuits, but this is an expensive and time-consuming task to be performed at the production line. Embedded calibration for mm-wave circuits is an appealing alternative to enhance yield that may overcome some of these issues. In this work we present a two-stage 60 GHz power amplifier (PA), designed in STMicroelectronics 55 nm CMOS technology, that features a one-shot calibration procedure for process variation compensation based on non-intrusive process monitors. We present the design of a tuning knob based on variable decoupling cells which have been implemented within the PA for calibration purposes. The proposed one-shot calibration procedure reads the output of the embedded process monitors and then relies on a machine learning regression model to find the best configuration of the tuning knobs for optimizing the performance of the circuit and enhance fabrication yield.

Conference - IEEE International Symposium on Circuits and Systems ISCAS 2019
F. Cilici, M.J. Barragan, S. Mir, E. Lauga-Larroze, S. Bourdel and G. Leger
A sub-μVRMS chopper front-end for ECOG recording  »
This paper presents a low-noise, low-power fully differential chopper-modulated front-end circuit intended for ECoG signal recording. Among other features, it uses a subthreshold source-follower biquad in the forward path to reduce noise and avoid the implementation of a ripple rejection loop. The prototype was designed in 0.18μm CMOS technology with a 1V supply. Post-layout simulations were carried out showing a power consumption below 2μW and an integrated input-referred noise of 0.75μVrms, with a noise floor below 50 nV/Hz, over a bandwidth from 1 to 200Hz, for a noise efficiency factor of 2.7.

Conference - IEEE International Symposium on Circuits and Systems ISCAS 2019
N. Pérez-Prieto, J.L. Valtierra, M. Delgado-Restituto and A. Rodríguez-Vázquez
Artifact-aware analogue/mixed-signal front-ends for neural recording applications  »
This paper presents a brief review of techniques to overcome the problems associated with artifacts in analog front-ends for neural recording applications. These techniques are employed for handling Common-Mode (CM) Differential-Mode (DM) artifacts and include techniques such as Average Template Subtraction, Channel Blanking or Blind Adaptive Stimulation Artifact Rejection (ASAR), among others. Additionally, a new technique for DM artifacts compression is proposed. It allows to compress these artifacts to the requirements of the analog front-end and, afterwards, it allows to reconstruct the whole artifact or largely suppress it.

Conference - IEEE International Symposium on Circuits and Systems ISCAS 2019
N. Pérez-Prieto, M. Delgado-Restituto and A. Rodríguez-Vázquez
A current attenuator for efficient memristive crossbars read-out  »
This paper presents a new current attenuator circuit to scale down the inference currents in memristor based crossbars that drive integrate-and-fire neurons, which subsequently allows to reduce the size of integrating capacitors by several orders of magnitude, making IC integration possible. The proposed circuit uses a linear switch to divide the inference current and scale it down by a factor of about 104. The proposed attenuator has been designed in 130nm CMOS technology. Simulation results considering noise, process and temperature variations are shown to validate the presented approach.

Conference - IEEE International Symposium on Circuits and Systems ISCAS 2019
C. Mohan, J.M. de la Rosa, E. Vianello, L. Perniola, C. Reita, B. Linares-Barranco and T. Serrano-Gotarredona

IMSE-related sites
Cl Américo Vespucio, 28. Parque Científico y Tecnológico Cartuja, 41092, Sevilla. Phone: +34 954466666, Fax: +34 954466600
Friday, 19 July 2019
Last update: 10.07.2019
  infoimse-cnmcsices

© Copyright 2019 IMSE-CNM
The information contained in this website is of a general nature and is provided for information purposes. It may contain unintentional errors or may be out-of-date. Unless otherwise stated, this information may be totally or partially reused as long as the source is cited and the update time is specified.
Notwithstanding, the use of the information available on this website must always comply with the regulations laid down by the Consejo Superior de Investigaciones Científicas (CSIC) for the use, distribution, publication or inclusion of this material in any medium or format accessible to third parties.
CSIC web legal notice