Consejo Superior de Investigaciones Científicas · Universidad de Sevilla
es    en
Next-Generation Sigma-Delta Converters: Trends and Challenges in a Digital-Driven World.
José M. de la Rosa
- Tyndall National Institute, Cork, Ireland.
27 Febrero 2018
- University College Dublin, Ireland.
26 Febrero 2018
♦ Quiero un proyecto europeo
¿Para qué un proyecto europeo? · Conocer H2020 · Interdisciplinariedad · Oportunidades · Programa Excelencia de H2020 · Ciclo de vida de un proyecto europeo · La Oficina General de Proyectos Internacionales (OGPI) de la US · Guía de recursos.
Oficina General de Proyectos Internacionales (OGPI) de la US
Facultad de Física
9 Febrero 2018
♦ Visitas al IMSE
IES Miguel Servet
8 Enero 2018
Stereovision in man, monkey and machine.
Benoit Cottereau, CNRS (France)
7 Febrero 2018

El Mundo de los Chips

Oferta de servicios basados en el sistema automático de test ATE Agilent 93000

El IMSE en los medios

Tríptico informativo

El IMSE en Linkedin

El IMSE en Linkedin

El IMSE en Digital.CSIC

El IMSE en Digital.CSIC

Últimas publicaciones
Memristors fire away  »
Neuromorphic computing based on fully memristive neural networks could offer a scalable and lower-cost alternative to existing neural spiking chips based solely on CMOS technology.

Journal Paper - Nature Electronics, vol. 1, no. 2, pp 100-101, 2018 NATURE
DOI: 10.1038/s41928-018-0028-x    ISSN: 2520-1131    » doi
B. Linares-Barranco
VLSI Design of Trusted Virtual Sensors  »
This work presents a Very Large Scale Integration (VLSI) design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a virtual sensor based on a configurable and programmable PieceWise-Affine hyper-Rectangular (PWAR) model. An algorithm is presented to find the best values of the programmable parameters given a set of (empirical or simulated) input-output data. The VLSI design of the trusted virtual sensor uses the fast authenticated encryption algorithm, AEGIS, to ensure the integrity of the provided virtual measurement and to encrypt it, and a Physical Unclonable Function (PUF) based on a Static Random Access Memory (SRAM) to ensure the integrity of the sensor itself. Implementation results of a prototype designed in a 90-nm Complementary Metal Oxide Semiconductor (CMOS) technology show that the active silicon area of the trusted virtual sensor is 0.86 mm 2 and its power consumption when trusted sensing at 50 MHz is 7.12 mW. The maximum operation frequency is 85 MHz, which allows response times lower than 0.25 μs. As application example, the designed prototype was programmed to estimate the yaw rate in a vehicle, obtaining root mean square errors lower than 1.1%. Experimental results of the employed PUF show the robustness of the trusted sensing against aging and variations of the operation conditions, namely, temperature and power supply voltage (final value as well as ramp-up time).

Journal Paper - Sensors, vol. 18, no. 2, article 347, 2018 MDPI
DOI: 10.3390/s18020347    ISSN: 1424-8220    » doi
M.C. Martínez-Rodríguez, M.A. Prada-Delgado, P. Brox and I. Baturone
Real-Time Inter-Frame Histogram Builder for SPAD Image Sensors  »
CMOS image sensors based on single-photon avalanche-diodes (SPAD) are suitable for 2D and 3D vision. Limited by uncorrelated noise and/or low illumination conditions, image capturing becomes nearly impossible in a single-shot exposure time. Moreover the depth accuracy is affected by jitter. Therefore, many frames need to be taken to reconstruct the final accurate image. The proposed reconstruction algorithm is based on pixel-wise histogram building. Specifically, a histogram is built on the fly for each pixel of the array from the ongoing acquired frames. This paper presents the design and implementation on FPGA of a real-time pixel-wise inter-frame histogram builder at 1kfps. The design has been proven with a 64×64-pixels SPAD camera. Its remarkable robustness has been demonstrated in harsh conditions such as 42 kHz of dark count rate (DCR) and high background illumination up to 20 times larger than the DCR. The system has a graphic user interface for 2D/3D imager configuration, image streaming and pixel-wise histogram streaming.

Journal Paper - IEEE Sensors Journal, vol. 18, no. 4, pp 1576-1584, 2018 IEEE
DOI: 10.1109/JSEN.2017.2784484    ISSN: 1530-437X    » doi
I. Vornicu, R. Carmona-Galan and A. Rodriguez-Vazquez
Guest Editorial-Special Issue on Selected Papers From IEEE BioCAS 2016  »
Abstract not avaliable

Journal Paper - IEEE Transactions on Biomedical Circuits and Systems, vol. 11, no. 6, pp 1256-1257, 2017 IEEE
DOI: 10.1109/TBCAS.2017.2779252    ISSN: 1932-4545    » doi
M. Delgado-Restituto, P. Mohseni and J. Ohta
Introduction to ACHIEVE: a European Training Network based on the experience of EUNEVIS  »
Abstract not avaliable

Conference - Workshop on the Architecture of Smart Cameras WASC 2017
R. Carmona-Galan

Webs relacionadas con el IMSE
Cl Américo Vespucio s/n, Parque Científico y Tecnológico Cartuja, 41092, Sevilla. Teléfono: 954466666, Fax: 954466600
martes, 20 de febrero de 2018
Última actualización: 16.02.2018

© Copyright 2018 IMSE-CNM
Los contenidos de estas páginas web tienen solo carácter informativo. Los datos que aparecen pueden contener errores o no estar actualizados.
La información disponible, salvo indicación expresa en contrario, es susceptible de ser reutilizada total o parcialmente siempre que se cite la fuente de los documentos y su fecha de actualización.
En cualquier caso, este uso se regirá de acuerdo con lo legalmente dispuesto por el Consejo Superior de Investigaciones Científicas para publicarla en cualquier soporte o para utilizarla, distribuirla o incluirla en otros contextos accesibles a terceras personas.
Aviso legal web CSIC