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A CMOS 0.8µ m Transistor-Only 10.5bit@1.63MHz@10kHz
Switched-Current Fourth-Order Bandpass  
Modulator
Team: José Manuel de la Rosa,
Belén Pérez-Verdú and Angel Rodríguez-Vázquez.
Date: 1997
| Physical Data |
- 0.8µ m CMOS n-well, double poly,
double metal.
- 0.48mm2 (excluding bonding pads).
- ~ 350 transistors.
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Electrical Data |
- Switched-Current fully-differential circuitry.
- 5V@65mW.
- 16MHz maximum clock frequency (on-chip).
- 540kHz-1.63MHz center frequency
- 10kHz bandwidth (AM commercial band)
- >57dB Dynamic Range (10.5bit).
- 50µ A peak input signal.
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Design Technique: |
- Automatized modulator and cell sizing.
- Full Custom.
- Switched-Current building blocks:
- Regulated-Folded Cascode Memory Cell
with CMFB.
- LDI loop resonator structure.
- Fast regenerative latched comparator.
- Current mode buffer to interface off-chip
currents.
- Layout strategies
- Guard rings, shielding, symmetry.
- Separate A and D supply lines.
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Features and Applications: |
- Fourth Order Single-loop architecture
- Bandpass A-to-D conversion for digital
AM radio receivers.
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Bandpass
Modulators (BPM)
have been demonstrated as basic building blocks for wireless Intermediate-Frequency
(IF) communications. A number of CMOS prototypes have been reported using
switched-capacitor (SC) circuits [Hair96],[Ong97].
However, very little has still been done on the design of this kind of
oversampled modulators using Switched-Current (SI) circuits [Rosa97].
The chip presented here is a SI fourth-order BPM
for converting AM signals. The modulator architecture has been obtained
by applying a 
transformation to a 2nd-order lowpass
modulator. Because of this transformation, the transfer function for the
quantization noise has two transmission zeroes at 
where 
is the clock frequency. The most basic linear block is a second generation
fully-differential regulated-folded cascode memory cell with Common Mode
Feedback Circuit (CMFB). This cell employes an input local feedback in
order to reduce the input impedance. Two extra MOSFET's connected to the
memory nodes are used to create a dominant pole and, thus, to control
the error due to incomplete settling. These extra capacitances reduce
also the common-mode charge-injection error. The memory cell has been
designed using a transistor-level optimizer [Mede95]
to attain the specifications required for AM digital radio receivers.
We have incorporated a single-ended to fully-differential high frequency
current mode buffer at the front end of the modulator. This buffer is
used to isolate the on-chip circuitry from parasitic time constants at
the chip input pads, thus allowing us to take full advantage of the speed
capabilities of current-mode circuits.
References:
- [Hair96] A.
Hairapetian, "An 81-MHz IF Receiver in CMOS", IEEE Journal
of Solid-State Circuits, pp. 1981-1986, Dec. 1996.
- [Ong97] A.K.
Ong, B.A. Wooley, "A Two-Path Bandpass
Modulator for Digital IF Extraction at 20MHz", Proc. of IEEE ISSCC97,
pp. 212-213, February 1997.
- [Rosa97] J.M. de la Rosa, B. Pérez-Verdú,
F. Medeiro and A. Rodríguez-Vázquez, "A 2.5MHz 55dB
Switched-Current BandPass
Modulator for AM Signal Conversion", Proc. of the 1997 European
Solid-State Cicuits Conference, pp. 156-159, September 1997.
- [Mede95] F.Medeiro,
B. Pérez Verdú, A. Rodríguez Vázquez,and
J.L. Huertas, "A Vertically-Integrated Tool for Automated Design
of
Modulators". IEEE Journal of Solid-State Circuits, Vol. 30, pp.
762-772, July 1995.
Images List:
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