|
|
|
A 13bit 2.2MSample/s 55mW CMOS  
Modulator
Team: Fernando Medeiro, Belén
Pérez-Verdú and Angel Rodríguez-Vázquez
Date: 1997
| Physical Data |
- 0.7µ m CMOS n-well, single-poly,
double metal
- 1.3mm2
(excluding pads)
- 500 transistors
|
Electrical Data |
- Switched-Capacitor fully-differential
circuitry
- 5-V supply @ 55mW
- 35.2-MHz clock frequency (on-chip phase
generation)
- 2.2-MSample/s output rate (1.1-MHz bandwidth)
- 79.5dB dynamic range (13bit)
- 74dB SNR-peak
- 1-V peak input signal
|
Design Technique: |
- Automatized modulator and cell sizing
- Analog full-custom, digital semi-custom
- Switched-Capacitor circuits:
- Optimized integrator weights for maximum
dynamic range and minimum output swing and dynamic requirements
- Integrators with phase delay feed-through
compensation
- Folded-cascode amplifier with low consumption
dynamic common-mode feedback net
- Fast regenerative latched comparators.
- Simple 3-bit flash ADC and resistive
ladder DAC
- Layout
- Guard rings, shielding, symmetry.
- Separate analog and digital supply
lines.
|
Features and Applications: |
- High-resolution, low-power modulator
based on a robust high-order cascade multi-bit architecture with
only X 16 oversampling
- Used in a ADSL high-speed modem for cooper-wire
data transmission
|
This
modulator uses multi-bit quantization in the last stage of a 2-1-1 cascade
architecture and single-bit quantization in the remaining stages (Fig
2)[Mede97]. Observing the relationships of (Fig
2b), the quantization error induced in the latter is cancelled in the
digital domain, so that under ideal conditions only the input signal and
the last-stage quantization error, which is fourth-order shaped, appear
at the modulator output. Non-linear behavior of last-stage DAC and other
circuit imperfections as amplifier finite DC-gain and integrator weight
mismatch degrade the modulator performance [Mede98].
However, it is shown that this architecture is less sensitive to the DAC
non-linearity than previously reported and that up to 3-bit quantization
can be used with relaxed building block specifications [Mede97][Mede98].
References:
- [Mede97] F.
Medeiro, B. Pérez-Verdú and A. Rodríguez-Vazquez:
"A 74dB DR, 1.1-MHz signal band 4th-order 2-1-1 cascade multi-bit
CMOS
modulator for ADSL", ESSCIRC'97, pp. 72-75, 1997.
- [Mede98] F. Medeiro, et al.: "Multi-bit
cascade
modulator for high-speed A/D conversion with reduced sensitivity to
DAC errors", Electronics Letters, Vol. 34, pp. 422-424, March 1998.
Images List:
|
|
