A 16.4bit, 9.6kSample/s 1.71mW CMOS Modulator

Figure 1: Die microphotograph

Figure 2: 2nd-order single-loop M

a) Schematic (Oversampling ratio = 256)	b) Estimated FOM to obtain 16bit at 9.6kS/s as a function of the oversampling ratio, using several modulator architectures.

Figure 3: Fully-differential SC schematic and clock phases

Figure 4: Fully-differential folded-cascode OTA and static CMFB net

Features: 80dB DC-gain, 20.7-MHz GB / 70degree PM for 1.2pF load, 30µ A output current, 5V output swing, 0.63mW power consumption.

Figure 5: Measurements

a) Modulator output spectrums: (I) for 0dBV, 1.25kHz input tone; (II) chopper compensation of the amplifier offset

b) Signal-to-(noise + distortion) ratio in the baseband (DC-4.8kHz) as a function of the input amplitude

c) Dynamic range (I), and Figure-of-Merit value (II) as a function of the oversampling ratio