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Real-Time Optimizer IC with Programmable Feasibility
Region
Team: Rafael Domínguez-Castro
and Angel Rodríguez-Vázquez
Date: May-1990
| Physical Data |
- 3.0µ m CMOS n-well, single-poly,
double metal.
- Dimensions of the core array: 5760mm
X 5440mm2
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Electrical Data |
- Power consumption@5v: 50mW
- Power rails. Nominal: 5V; Minimum: 4V.
- Operating frequency: 200kHz
- Processing time: < 500µ s
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Design Technique |
- Summers and Integrators using the Switch
Capacitor technique.
- Summers and Integrators topologies are
insensitive to the opamp's offsets.
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Features and Applications |
- The chip find the minimum of a bidimensional
programable constrained linear problem.
- Implement a modified version of the outer
penalty technique.
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Multiparameter optimization is the process
of finding a point of a parameter space x = {x1,
x2, ... xN}T
where a cost function (x)
is minimized. Most commonly, this cost function contains information about
the problem target and the constraints that the solution point has to
meet (constrained optimization). These constraints define the a region
of the design space where the solution point has to be comprised -- called
feasibility region.
The fastest way to realize optimization in
practice is through the implementation of a companion dynamic gradient
system,
Which for given initial point xo
obtains the nearest point where the cost function has a local minimum
-- the only problem solution for monotonic cost functions.
This companion dynamic system can be implemented
as a program on a digital computer, and then solved in serial form --
not suitable for applications where high-speed is a must, as for instance
robotics, satellite guidance, etc. This chip parallelizes the solution
procedure through the use of a dedicated computing artifacts whose internal
operation is analog, while its control is fully digital.
The chip uses switched-capacitor circuit
design techniques and encompasses an innovative multiplexing architecture
to reduce the circuitry area overhead and thus, increase the complexity
of problems that can be mapped on a single piece of silicon. For more
information please see [Rodr88], [Rodr90], [Domi92],
[Domi93].
References:
- [Rodr88] A. Rodríguez-Vázquez,
A.Rueda, J.L. Huertas and R. Domínguez-Castro: "Switched-Capacitor
Neural Networks for Linear Programming". Electronics
Letters, Vol.. 24, pp 496-498, IEE April 1988.
- [Rodr90] A. Rodríguez-Vázquez,
R. Domínguez-Castro, A. Rueda, J.L. Huertas and E. Sánchez-Sinencio:
"Nonlinear Switched-Capacitor Neural Networks for Optimization
Problems". IEEE Trans. Circuits and Systems,
Vol. 37, pp. 384-398, March 1990.
- [Domi92] R. Domínguez-Castro, A. Rodríguez-Vázquez,
J.L. Huertas and E. Sánchez-Sinencio: "Analog Neural Programmable
Optimizers in CMOS VLSI Technologies". IEEE
Journal of Solid-State. Circuits, Vol. 27, pp. 1110-1115, July
1992.
- [Domi93] R. Domínguez-Castro:
"Optimizadores Neuronales Usando Circuitos Analógico-Digitales",
Tesis Doctoral, Dpto. Electricidad. y Electrónica., U. Sevilla,
1993.
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