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CNNUC_2
Team: Rafael Domínguez-Castro,
Servando Espejo Meana, Angel Rodríguez-Vázquez and Ricardo
Carmona Galán.
Date: 1994
| Physical Data |
- 0.8µ m CMOS n-well, single-poly,
double metal.
- 20x22 array of processors.
- Cell Size: 190x190µ m.
- Cell density: 27.5cell/mm2.
- Area of the core array: ~16mm2.
- Chip Area: 30mm2.
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Electrical Data |
- Power consumption@5v: <5W
- Power rails. Nominal: 5V; Minimum: 4.5V.
- Operating Frequency: 10MHz
- Time constant: 0.4µ s
- Fotosensor current (Darlington): ~0.8µ
A @ 615 lux.
- Weights range: 7bits + sign
- Weights accuracy: ~1%
- Programmable analog coefficients: 19
- Programmable logic values: 4
- Processing time: Task dependent. <
10µ s.
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| Design Technique |
- Continuous time implementations of the
FSR model.
- Analog operation and digital control.
- Self tuning External Management of the
chip is completely digital.
- Analog weights are specified and internally
stored in digital form.
- Adaptive stages transform the digital
weight code into an analog voltage and perform a synapse's nonlinearity
compensation.
- The synapse is implemented with four
transistor in ohmic region plus two buffers. Hence a eight transistors
synapse is used.
- A time multiplexing strategy half de
required synapses.
- Fully differential architecture.
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Features and Applications |
- Input images can be uploaded in electrical
and optical form, (binary).
- Output images are downloaded in electrical
form, (binary).
- Programmability is complete with a neighborhood
radius of 1.
- A program memory stores up to eight microinstructions,
which can be selected in any order any number of times
- Accuracy is around 7-8 bits in weight
values. Offset is cancelled internally.
- The optical input offers the possibility
of using the chip without a conventional camera for vision task,
such a texture detection and motion detection and estimation.
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This paper presents a CMOS chip for the parallel
acquisition and concurrent analog processing of 2-D binary images. Its
processing function is determined by a reduced set of analog coefficients
(19) whose values are programmable with 7bit accuracy. The internal programming
signals are analog, but the external control interface is fully digital.
On-chip nonlinear DACs map digitally-coded weight values into analog control
signals, using feedback to pre-distort their transfer characteristics
in accordance to the response of the analog programming circuitry. This
strategy cancels out the non-linear dependence of the analog circuitry
with the programming signal, and reduces the influence of inter-chip technological
parameters random fluctuations. The chip includes a small digital RAM
memory to store eight set of processing parameters in the periphery of
the cell' array, and four 2-D binary images spatially-distributed over
the processing array. It also includes the necessary control circuitry
to realize the stored instructions in any order, and also to realize programmable
logic operations among images. The chip architecture is based on the Cellular
Neural/Nonlinear Network Universal Machine (CNN-UM). It has been fabricated
in a 0.8µ m single-poly double-metal technology and features 2µ
s operation speed (time required to process an image) and around 7bit
accuracy in the analog processing operations.
More details can be found in
[Domi97].
References:
- [Domi97] R. Domínguez-Castro,
S. Espejo, A. Rodríguez-Vázquez, R. Carmona, Péter
Földesy, Ákos Zarándy, Péter Szolgay, Tamás
Szirányi and Tamás Roska: "A 0.8µ m CMOS 2-D
Programmable Mixed-Signal Focal-Plane Array Processor with On-Chip Binary
Imaging and Instructions Storage". IEEE J.
Solid-State Circuits, Vol. 32, pp. 1013-1026, No. 7, July 1997.
Images List:
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