High-Resolution CMOS Current Comparators

Team: Rafael Domínguez-Castro and Angel Rodríguez-Vázquez

Date: February-1990

knowledge of the mechanisms underlying the operation of this block. It requires using nonlinear characteristics with well controlled breakpoints and sharp transitions, which are better realized using feedback structures. Also, the self tracking provided by these feedback structures guarantee robust high resolution (<1pA) and low offset (<1pA) operation in a standard VLSI CMOS technology. Essentially, for current comparator design purposes we must look for mechanisms that provide transimpedance gain.

Figure shows a conceptual circuit for the basic gain mechanism available in CMOS technology, consisting of a VCCS modeling the MOS transistor transconductance, a linear resistor accounting for the device's equivalent Early voltage, and a capacitor modeling the finite gain-bandwidth product. A current sensing stage must be used in the front for current-to-voltage amplification, as shown in the figure, where a general sensing component is considered, represented as an impedance Z.

There are many possible design choices for Z, depending on whether it is predominately resistive or capacitive. The nominal extreme cases correspond to those using either purely resistive input, as is the case for the conventional current comparator architecture, proposed by Freitas and Current [Frei83], or purely capacitive input, but in practice the input node will be neither purely resistive nor purely capacitive, due to parasitics.

Routine analysis obtains the following expression for the output voltage waveform:

that can be simplified for the case of purely resistive input as

and in the other case, for purely capacitive input can be obtained

The first approach is better for large input current but the second is better for small level of current. We are obtained a comparator which combines capacitive input current sensing for high resolution and increased speed, with nonlinear feedback to reduce input voltage variations and increase the useful current range. This circuits exhibit a capacitive input behavior for low level of current and a resistive input for large input current.

The performance of this circuit is demonstrated using a 2µ m CMOS prototype with a measured input current comparison range of 140dB, resolution and offset below 10pA, and an operation speed approximately two orders of magnitude better than that of conventional circuits. Different measurements showing this performance are showed in the next figure.

For more information please see [Rodr92], [Rodr93], [Rodr95] and [Liña97].

References:

1. [Frei83] D.A. Freitas and K.W. Current: "CMOS Current Comparator Circuit". Electronics Letters, Vol. 19, pp 695-697, Aug. 1983.
2. [Rodr92] R. Domínguez-Castro, A. Rodríguez-Vázquez, F. Medeiro and J.L. Huertas: "High-Resolution CMOS Current Comparators". 1992 European Solid-State Circuits Conf, ISBN 87-984232-0-7, pp. 242-245, Kandrup 1992.
3. [Rodr93] A. Rodríguez-Vázquez, S. Espejo, R. Domínguez-Castro and J.L. Huertas : "Current Mode Techniques for the Implementation of Continuous and Discrete-Time Cellular Neural Networks". IEEE Transactions on Circuits and Systems, Vol. 40, pp. 132-146, IEEE March 1993.
4. [Rodr95] A. Rodríguez-Vázquez, R. Domínguez-Castro, F. Medeiro, J.L. Huertas and M. Delgado-Restituto: "High-Resolution CMOS Current Comparators: Design and Applications to Current-Mode Function Generation". Analog Integrated Circuits and Signal Processing, Vol.7, Kluwer Academics, pp. 149-165, 1995.
5. [Liña97] G. Liñán-Cembrano, R. del Río-Fernández, R. Domínguez-Castro and A. Rodríguez-Vázquez: "A Robust High-Accuracy High-Speed Continuous-Time Current Comparator". Electronics Letters, Vol. 33, pp. 2082-2084, December 1997.

Images List:

• Figure 1: Chips Microphotographs

• Figure 2: Basic CMOS gain mechanisms: (a) Voltage amplification, (b) Transimpedance amplification.

• Figure 3: Experimental Results