A Random Access Analog Memory Chip for Real-Time Image Processing

Team: Ricardo Carmona, Servando Espejo, Rafael Domínguez-Castro and Angel Rodríguez-Vázquez

Date: January 1998

Data compressing and coding and communications in object oriented multimedia applications like telepresence, computer-aided medical diagnosis or telesurgery require an enormous computing power in the order of Trillion Operations per Second (TeraOPS). Compared with conventional digital technology, Cellular Neural/Nonlinear Network (CNN) based computing is capable of realizing these TeraOPS-range image processing tasks in a cost-effective implementation. To exploit the computing power of the CNN Universal Machine (CNN-UM), the CNN Chipset architecture (Fig 2) has been developed a mixed-signal hardware platform for CNN-based image processing. One of the non-standard components of the chipset is the cache memory of the analog array processor, the Analog Random Access Memory (ARAM). This ARAM chip that has been designed and fabricated in a 0.5µ m CMOS technology (Fig 1). This chip consists of a fully addressable array of 32x256 analog memory registers and has a packing density of 637 analog-memory-cells/mm2 (Fig 3). Random and non-destructive access of the memory contents is available. Bottom-plate sampling techniques have been employed to eliminate harmonic distortion introduced by signal-dependent feedthrough. Signal coupling and interaction have been minimized by proper layout measures, including the use of protection rings and separated power supplies for the analog and the digital circuitry. The prototype features an equivalent resolution of up to 7 bits measured by comparing the reconstructed waveform with the original input signal. Measured access times for writing /reading to/from the memory registers are 200ns and 800ns, respectively (Fig 4). I/O rates via the 16-lines I/O bus exceed 10Msamples/s. Storage time at room temperature is in the 80 to 100ms range, without accuracy loss.

More details are available in the following papers:

References:

1. [Carm98] R. Carmona, S. Espejo, R. Domínguez-Castro, A. Rodríguez-Vázquez, T. Roska, T. Kozek and L. O. Chua, "A 0.5µm CMOS CNN Analog Random Access Memory Chip for Massive Image Processing". Proc. of the Fifth IEEE Int. Workshop on Cellular Neural Networks and their Applications, pp. 243-248, London, UK, April 1998.
2. [Carm99] R. Carmona, S. Espejo, R. Domínguez-Castro, A. Rodríguez-Vázquez, T. Roska, T. Kozek and L. O. Chua, "A 0.5µm CMOS Random Access Analog Memory Chip for TeraOPS Speed Multimedia Video Processing". IEEE Transactions on Multimedia. (Accepted for publication in 1999).

Images List:

• Figure 1: Analog RAM prototype chip microphotograph

• Figure 2: CNN Chipset architecture

• Figure 3: Circuits and System design

• Figure 4: Test measurements

• Figure 5: Tests with real images