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CMOS Optoelectronic IC for Real-Time Extraction of
Image Features
Team: Ricardo Carmona,
Servando Espejo, Rafael Domínguez-Castro and Angel Rodríguez-Vázquez
Date: November, 1994
| Physical Data |
- 1.5µ m CMOS n-well, single poly,
double metal
- 5021µ m x 5799µ m
- 8 x 104
transistors approx.
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Electrical Data |
- Current-mode operation
- Optical input capability
- 380mW @ 5V
- Digitally-controlled function
- 10MHz master clock frequency
- CNN settling time: 3.2µ s
- 28.8µ s for the complete operation
including I/O and 4 Connected Component Detections.
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Design Technique: |
- Analog full-custom.
- Current-mode integrators with self-limited
state current.
- Cascode composite transistors with optimum
biasing.
- Light regulation through collective computation
circuitry.
- Parallel dowloading with I-V output buffers.
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Features and Applications: |
- Monolithic realization of cellular neural
networks.
- Concurrent image acquisition and preprocessing
for feature extraction.
- Character recognition.
- Document analysis.
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The incorporation of preprocessing circuitry
at the sensory plane in image processing systems enables the reduction
of the amount of output data from the sensor array, and hence, increases
the throughput rate in those applications limited by data-transmission
rate. In particular, smart-pixel chips incorporate an analog computing
cell at each sensory point, achieving high speed and low area occupation
in the combined sensing/processing functions by exploiting parallelism
(Fig 2). Each unit (smart-pixel) senses a point of the input image and
interacts with other units in the neighborhood to perform parallel-processing
tasks on the input image. In this manner, the transmission path between
the sensing and preprocessing areas is eliminated, and in those applications
requiring a subsequent high-level processing, the amount of data transmitted
to the external processor is significantly reduced. Smart-pixel chips
are of strong practical interest in pattern recognition problems, where
features detection in the input image are crucial. Connected component
detection consists of counting the number of connected pieces encountered
by scanning an input image in a given direction (Fig 4). Pattern recognition
can be realized by processing the data obtained after performing this
task in different directions. The paradigm of Cellular Neural Networks
is a very suitable framework for the systematic design of smart-pixel
chips. This chip makes use of a modified CNN model which results in improved
speed/power and area figures as compared to previous CNN implementations.
More details are available in the following papers:
References:
- [Espe94a] S.
Espejo, R. Domínguez-Castro, R. Carmona, A. Rodríguez-Vázquez.
"A Continuous-time Cellular Neural Network Chip for Direction-selectable
Connected Component Detection with Optical Image Acquisition".
Fourth International Conference on Microelectronics for Neural Networks
and Fuzzy Systems (MICRONEURO'94), pp. 383-391, Turin, Italy, September
1994.
- [Espe94b] S. Espejo, R. Domínguez-Castro,
R. Carmona, A. Rodríguez-Vázquez. "Cellular Neural
Network Chips with Optical Image Acquisition". 1994 International
Conference on Neural Networks (ICNN'94), vol. III, pp. 1877-1882, Orlando
Florida, USA, June 1994.
- [Carm94] R. Carmona, S. Espejo, R. Domínguez-Castro,
A. Rodríguez-Vázquez. "CNN Reconfigurable para Sensado
y Procesamiento de Imágenes Binarias mediante la Detección
de Componentes Conectados". IX Congreso de Diseño de Circuitos
Integrados (DCIS'94), pp. 191-196, Gran Canaria, Noviembre 1994.
Images List:
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