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CMOS Optoelectronic IC for Radon Transform of Binary Images Team: Ricardo Carmona, Servando Espejo, Rafael Domínguez-Castro and Angel Rodríguez-Vázquez Date: October, 1993
The parallel-computation paradigm of Cellular Neural Networks provides a very suitable framework for systematic development of sensory processing chips. CNNs are uniform, two-dimensional arrays of locally-interconnected analog cells, one per pixel. Their practical application requires systems with a large number of cells, and hence, VLSI implementation is crucial. The local connectivity property avoids the otherwise common problem of neural networks realization: huge routing area. However, the objective of maximizing the number of cells in the system represents a trend in the field of analog design. In addition, the high input and output throughputs desirable on such highly-parallel processing systems provides another open field for future, better solutions.The area, power and speed figures obtained from this prototype are quite competitive as compared to previous CNN implementations (Fig 2). Furthermore, the optical sensing devices provide fully-parallel input-transmission capability. The incorporation of preprocessing circuitry at the sensory plane in image processing systems enables the reduction of the amount of output data from the sensor array, and hence, increases the throughput rate in those applications limited by data-transmission rate (Fig 3). In particular, smart-pixel chips incorporate an analog computing cell at each sensory point, achieving high speed and low area occupation in the combined sensing/processing functions by exploiting parallelism. Each unit (smart-pixel) senses a point of the input image and interacts with other units in the neighborhood to perform parallel-processing tasks on the input image.
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