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A Random Access Analog Memory Chip for Real-Time Image
Processing
Figure 1: Analog RAM prototype chip
microphotograph
Figure 2: CNN Chipset architecture
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a) CNN Chipset architecture |
b) Pipelined system with
interleaved ARAM chips |
Figure 3: Circuits and System
design
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a) ARAM Chip architecture |
b) Video signal interface
to the CNN chipset |
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c) I/O MUX/DEMUX |
d) Bottom-sampling S/H
line schematics |
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a) Poly-over-diffusion
capacitor |
b) Speed-accuracy trade-off |
Figure 4: Test measurements
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a) Reconstructed waveform |
b) Root-mean-square error |
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c) FFT of the output signal
for a 10KHz input sinewave sampled at 250KHz |
d) Stored voltage degradation
(24 cells) |
Figure 5: Tests with real
images
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32 X 256 -pixel
input |
output: 256 gray levels |
abs(diff) |
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512 X 512
-pixel input |
output: 256 gray levels |
abs(diff) |
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512 X 512
-pixel input |
output: 256 gray levels |
abs(diff) |
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512 X 512
-pixel input |
output: 256 gray levels |
intensified abs(diff) |
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