|
|
|
A 13-bit 4-MSample/s 77-mW CMOS  
Modulator
Team: Rocío del Río,
Fernando Medeiro, Belén Pérez Verdú, and Ángel
Rodríguez Vázquez
Date: 2000
| Physical Data |
- 0.35µ m CMOS n-well, single-poly,
five metals
- 1.32mm2 (excluding pads)
- 1500 transistorscaráteristica
|
Electrical Data |
- Switched-Capacitor fully-differential
circuitry
- 3.3-V supply @ 77mW
- 64-MHz clock frequency (on-chip phase
generation)
- 4-MSample/s output rate (2-MHz bandwidth)
- 78.4dB dynamic range (12.7bit)
- 72dB SNR-peak
- 1.1-V peak input signal
|
Design Technique |
- Automatized modulator and cell sizing.
- Analog full-custom, digital semi-custom.
- Switched-Capacitor circuits:
- Optimized integrator weights for maximum
dynamic range and minimum output swing and dynamic requirements.
- Integrators with phase delay feed-through
compensation.
- Two-stage Miller-compensated and folded-cascode
amplifiers with low consumption dynamic common-mode feedback net.
- Fast regenerative latched comparators.
- Simple 4-bit flash ADC and resistive
ladder DAC.
- Layout:
- Guard rings, shielding, symmetry.
- Separate analog and digital supply
lines.
|
Features and Applications |
- High-resolution,
low-power modulator based on a robust high-order cascade multi-bit
architecture with only
oversampling.
- Used in a
ADSL high-speed modem for cooper-wire data transmission.
|
This
modulator uses multi-bit quantization in the last stage of a 2-1-1 cascade
architecture and single-bit quantization in the remaining stages [Rio00].
The quantization error induced in the latter is cancelled in the digital
domain, so that under ideal conditions only the input signal and the last-stage
quantization error, which is fourth-order shaped, appear at the modulator
output. Non-linear behavior of last-stage DAC and other circuit imperfections
as amplifier finite DC-gain and integrator weight mismatch degrade the
modulator performance [Mede98]. However, it
is shown that this architecture is less sensitive to the DAC non-linearity
than previously reported and that up to 4-bit quantization can be used
with relaxed building block specifications [Rio00],[Mede98].
References:
- [Rio00] R. del
Río, F. Medeiro, B. Pérez-Verdú, and A. Rodríguez-Vázquez:
"High-Order Cascade Multibit SD Modulators for xDSL Applications".
Proc. Int. Symp. Circuits and Systems (ISCAS'2000), vol. 2, pp. 37-40,
Geneva, May 2000.
- [Mede98] F. Medeiro, B. Pérez-Verdú,
and A. Rodríguez-Vázquez: "Top-Down Design of High-Performance
Modulators". Kluwer Academic Publishers, Boston, November 1998.
Images List:
|
|
